Astera Labs Inc.
Principal Digital Design Engineer
San Jose, California, United States · Principal
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About the role
- Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™
- semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their
Responsibilities
- Develop and implement complex digital blocks and subsystems by defining micro-architecture and driving digital design.
- Lead efforts to achieve timing closure and implement Design-for-Test (DFT) features for optimal design performance.
- Mentor junior engineers to develop their technical skills and expertise.
- Drive designs to production, ensuring accountability for quality, schedule, and overall design success.
- Join our team as Principal Digital Design Engineer to architect and implement next-generation digital designs for high-performance connectivity solutions.
- You'll own complex blocks from micro-architecture through silicon bring-up, driving RTL implementation and collaborating with verification, PD and DFT teams to deliver high-performance products in a fast-paced, collaborative environment.
Requirements
- Bachelor's degree in electrical engineering or equivalent.
- Production experience with advanced CMOS nodes (≤7nm)
- Deep expertise in at least one high-speed protocol-PCIe, Ethernet, InfiniBand, DDR, or similar
- Proficiency with Cadence and/or Synopsys digital design flows
- Familiarity with UVM-based verification methodologies.
- Silicon bring-up, debug, and failure analysis expertise
- Strong work ethic with the ability to balance multiple priorities in a dynamic environment
- Customer-focused mindset with ability to translate business needs into technical excellence
Nice to have
- Hands-on collaboration with embedded firmware teams
- deep understanding of firmware development challenges and constraints
- Familiarity with standard embedded processor subsystems (RISC-V, Arm, etc.)
Skills
- Work closely with post-silicon teams to facilitate silicon bring-up and debug.
- Actively contribute to the development and improvement of silicon development processes.
Compensation
- The base salary range is $185,000.00 USD – $230,000.00 USD.
Benefits
- Collaborate with verification teams to develop test plans, achieve coverage closure, and debug complex issues.
This listing is sourced directly from Astera Labs Inc.'s careers page and normalized into a canonical job model.