Altera
Physical Design Lead — Execution
San Jose, California, United States · Principal
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About the role
- As an independent FPGA leader, we combine decades of silicon expertise with a startup's focus on speed and innovation.
- This role sits on Altera's senior individual-contributor (IC) technical ladder.
- Escalation & problem-solving - Serve as the escalation point for execution blockers, driving fast, pragmatic resolution under schedule pressure.
Responsibilities
- Principal Engineer) to drive the day-to-day physical design execution and delivery that gets Altera's chips across the finish line.
- You will be the connective tissue between physical design blocks and full-chip integration, with a clear growth path toward owning full-chip implementation scope.
- Execution ownership - Drive day-to-day physical design execution and delivery across blocks and full-chip integration, from floorplan through tapeout.
- Schedule & quality - Own the schedule and quality bar for physical design execution, proactively identifying risk and driving mitigation before it threatens a milestone.
- Cross-block coordination - Coordinate execution across multiple blocks and design teams, resolving conflicts and dependencies so full-chip closure stays on track.
- Process discipline - Partner with methodology and CAD teams to ensure execution practices stay aligned with signoff standards and quality gates.
- Mentorship - Mentor physical design engineers on execution best practices, prioritization, and schedule management.
- Design teams that look to you as the steady execution authority when timelines get tight.
- Scope growth - Grow into ownership of full-chip implementation scope, building the technical judgment and organizational relationships that role demands.
- Customer engagement - Engage senior customer technical stakeholders directly, building rapport and navigating challenging technical conversations with credibility, diplomacy, and influence.
Requirements
- Hands-on proficiency with industry-standard implementation and signoff tools - Synopsys Fusion Compiler / ICC2 / PrimeTime, Cadence Innovus / Tempus / Voltus, Ansys RedHawk-SC, Siemens Calibre, or equivalent.
- Experience with every tool is not required.
- Scripting and automation proficiency (Python, Tcl, Perl, or shell) sufficient to build and debug execution tooling, not only to run it.
- We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.
- Applicants must be eligible for any required U.S. export authorizations.
- Bachelor's, Master's, or PhD degree in Electrical Engineering, Computer Engineering, or a related field, plus 15+ years (Sr. Principal Engineer) or 12+ years (Principal Engineer) of physical design experience, including a minimum of four full-chip tapeouts at advanced nodes with direct execution ownership.
- A strong physical design execution track record, with direct accountability for schedule and quality outcomes across blocks and full chip.
- Demonstrated ability to deliver under schedule pressure without compromising quality, including experience managing critical-path recovery.
- Hands-on expertise across the physical design flow - floorplanning, placement, clock-tree synthesis, routing, and timing/power closure - and how these interact with signoff.
- Production physical design execution experience at [CONFIRM
- Hands-on proficiency with industry-standard implementation and signoff tools - Synopsys Fusion Compiler / ICC2 / PrimeTime, Cadence Innovus / Tempus / Voltus, Ansys RedHawk-SC, Siemens Calibre, or equivalent. Experience with every tool is not required.
- Experience driving execution on designs of high complexity with concurrent block teams across multiple sites.
- Demonstrated ability to engage senior customers, build rapport, and navigate challenging technical conversations with credibility, diplomacy, and influence.
- Strong organizational and cross-team coordination skills, with a track record of resolving conflicting priorities across design teams.
- Excellent communication skills, equally comfortable presenting to engineering teams and to senior stakeholders, internal and external.
Nice to have
- Experience mentoring or informally leading execution teams without formal management authority.
- Shift 1 (United States of America)
- San Jose, California, United States
- Posting Statement:
- Bachelor's, Master's, or PhD degree in Electrical Engineering, Computer Engineering, or a related field, plus 15+ years (Sr.
Compensation
- The pay range below is for Bay Area California only.
- Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc.
- We also offer incentive opportunities that reward employees based on individual and company performance.
- $231,500 - $341,075 USD
Company info
- Altera offers the scale and technical depth of an established silicon leader with the speed, ownership, and impact of a growth-stage company.
- Our engineers work at the edge of process technology and design methodology to deliver silicon that customers can trust, on schedule, every time.
- We are looking for a Physical Design Lead - Execution (Principal/Sr.
- On our senior IC ladder, your influence is measured by the designs you deliver and the trust you build - with customers and with your teams - not the size of a team you manage.
This listing is sourced directly from Altera's careers page and normalized into a canonical job model.