Astera Labs Inc.
Tech Lead, Digital Design Engineer
San Jose, California, United States · Senior
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About the role
- Astera Labs is seeking a Tech Lead Engineer to drive front-end digital design for high-performance switch ASICs that enable rack-scale AI infrastructure. In CCE2, you will translate microarchitecture into robust RTL and lead block-level execution across synthesis, timing, verification, DFT, and physical implementation.
- This is an opportunity to own critical connectivity technology from architecture through GDS while partnering across design, verification, physical design, and systems teams. You will help advance scalable fabric solutions built around UALink, UCI, PCIe Gen 6/7, ESUN, and Ethernet as Astera Labs continues to deliver purpose-built connectivity for demanding AI workloads.
- In CCE2, you will translate microarchitecture into robust RTL and lead block-level execution across synthesis, timing, verification, DFT, and physical implementation.
Responsibilities
- Define microarchitecture and implement synthesizable RTL for complex switch ASIC blocks.
- Develop front-end design solutions for high-performance networking and server connectivity applications.
- Drive block-level execution through synthesis, timing closure, gate-level simulation, DFT, and GDS delivery.
- Analyze design tradeoffs across performance, power, area, and schedule, and resolve implementation issues with cross-functional partners.
- Apply Synopsys and/or Cadence digital design flows to deliver production-quality silicon.
- Support silicon bring-up, lab debug, and root-cause analysis for complex connectivity issues.
- Astera Labs is seeking a Tech Lead Engineer to drive front-end digital design for high-performance switch ASICs that enable rack-scale AI infrastructure.
- This is an opportunity to own critical connectivity technology from architecture through GDS while partnering across design, verification, physical design, and systems teams.
Requirements
- Bachelor's degree in Electrical Engineering or a related field.
- 5-8 years of experience developing or supporting complex SoC or silicon products for switch ASIC, networking, server, or storage applications.
- Hands-on experience with high-speed protocols, including UALink, UCI, PCIe Gen 6/7, ESUN, and Ethernet.
Nice to have
- Master's degree in Electrical Engineering or a related field.
- Silicon bring-up and debug experience in small-geometry CMOS technologies at 28nm or below.
- Scripting experience with Python or comparable programming languages, along with a collaborative, customer-focused approach.
Skills
- Digital Architecture and RTL Design
- Integrate and configure reusable IP while ensuring clean interfaces, performance, and maintainability.
- Design Implementation and Signoff
- Verification, Bring-Up, and Technical Leadership
- Provide technical leadership, prioritize multiple workstreams, and communicate risks and progress clearly to stakeholders.
Compensation
- Salary range is $175,500 to $195,000 depending on experience, level, and business need.
Benefits
- Partner with design verification engineers to define plans, debug failures, and improve coverage using UVM-based methodologies.
Visa & Work Authorization
- Authorized to work in the United States.
This listing is sourced directly from Astera Labs Inc.'s careers page and normalized into a canonical job model.