Cisco
Director - ASIC Engineering (Technical Planning and Engineering Execution)
San Jose, California, US · Director · Full-time
Stay score
odds of building a lasting career here
Sponsors, but it's cap-subject — you still face the weighted lottery (~61% per draw at Level IV). Good if you win; have a cap-exempt backup on your list.
Lottery odds assume a STEM candidate.
Personalize to your clock →H-1B wage level
the lottery is wage-weighted — each level is one more entry
$5,053 more — $255,653 — moves this role to Level IV and 4 lottery entries. That figure is inside the range the employer already advertised.
Based on the DOL prevailing wage for this occupation and worksite, a base salary of $255,653 would place this position at wage Level IV. That figure is within the posted range, and I'd like to target it. This role classifies under "Software Developers" for prevailing-wage purposes.
DOL prevailing wage, 2026-27 wage year · Software Developers (15-1252) · San Jose-Sunnyvale-Santa Clara, CA. Wage level is derived by USCIS from the offered wage, occupation and worksite; the occupation shown is inferred from the job title.
Employer immigration record
from this employer's Department of Labor filings
Green-card filing pattern in this occupation
Green-card follow-through: 93%
Files H-1B transfers
Sourced from Department of Labor LCA, PERM and prevailing-wage disclosure data. Employer matching is by name, so figures may be split across an employer's legal entities. Absence of a filing means none appears in our copy of the data, not that none exists.
Community outcomes
No reports yet — be the first to help the next applicant.
About the role
- Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training.
Responsibilities
- In this strategic leadership role, you will serve as the operational backbone and Chief of Staff for the ASIC Physical Design (PD) & CAD engineering organization within the Silicon One Group, partnering directly with engineering heads, technical leads, and multi-functional executives to align operational execution, multi-million-dollar resource investments, foundry relations, and team culture.
- You will provide operational governance, multi-functional bridge-building, and strategic leadership across three key pillars:
- Analyze and optimize resource allocation across concurrent chip tape-outs, advanced process nodes, and next-generation technology exploration teams.
- Serve as the primary point of contact and operational bridge between the ASIC engineering team and key internal partners, including Product Management, Supply Chain / Foundry Operations, Software/Firmware teams, and HR.
- Partner with engineering leads to manage operational relationships, delivery schedules, and landmark commitments with external IP vendors and leading commercial foundries (e.g., TSMC, Samsung, Intel Foundry Services).
- Collaborate with engineering managers and HR on strategic hiring plans, technical skill-gap assessments, retention strategies, and workforce globalization initiatives.
- Design and implement internal communications, All-Hands meetings, and technical engineering summits to foster a transparent, high-performing, and collaborative engineering culture.
- Lead high-priority, ambiguous initiatives on behalf of the engineering head, such as evaluating geographic site expansions or exploring next-generation methodology adoptions (e.g., EDA tools).
- Drive the operational cadence (weekly, monthly, and quarterly business reviews) for the ASIC PD CAD organization.
Requirements
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical subject area or equivalent practical work experience.
- Experience in one or more of these areas Technical Program Management (TPM), Engineering Management, Business Operations, or Chief of Staff role within a hardware or semiconductor engineering environment.
- Experience managing engineering operational budgets, headcount allocations, or EDA tool licensing portfolios.
Nice to have
- Master of Business Administration (MBA) or Master's/Ph.D. degree or equivalent experience in Electrical Engineering, Computer Engineering, or a related field.
- Strong financial acumen with a proven track record managing multi-million-dollar operational budgets, EDA vendor contract negotiations, and complex multi-project resource models.
- Direct experience managing operational relationships, tape-out work, and commercial engagements with external semiconductor foundries (TSMC, Samsung, IFS) and third-party IP vendors.
- Proven ability to translate granular technical data (e.g., timing closure bottlenecks, yield metrics) into strategic executive business summaries.
- Proven ability to balance high-level organizational strategy with tactical problem solving to unblock operational bottlenecks.
- We work as a team, collaborating with empathy to make really big things happen on a global scale.
- Because our solutions are everywhere, our impact is everywhere.
- Message to applicants applying to work in the U.S. and/or Canada:
Compensation
- Lead the annual and long-range headcount, operating budget, and EDA tool licensing planning cycles in close partnership with Finance and Procurement.
Benefits
- Rigorously track program achievements, tape-out schedules, and silicon health metrics.
Company info
- We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow.
- At Cisco, we're revolutionizing how data and infrastructure connect and protect organizations in the AI era - and beyond.
- These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.
This listing is sourced directly from Cisco's careers page and normalized into a canonical job model.