Altera
Senior FPGA Circuit Design Engineer
San Jose, California, United States · Senior
Sponsorship not specified$149k-$215kDetected 19 days ago
FPGAElectrical EngineeringHardware DesignLeadershipMentoring
Stay score
odds of building a lasting career here
61Sponsors, lottery-bound
Cap-exempt (no lottery)0
Sponsors this role90
Entry-level history0
PERM / green-card track0
Lottery odds (Level IV)94
Fits your clock70
Sponsors, but it's cap-subject — you still face the weighted lottery (~61% per draw at Level IV). Good if you win; have a cap-exempt backup on your list.
Lottery odds assume a STEM candidate.
Personalize to your clock →H-1B wage level
the lottery is wage-weighted — each level is one more entry
Level I$124,4051 entry
Level II$155,8962 entries
Level III$187,4083 entries
Level IV$218,8994 entries
$6,796 more — $155,896 — moves this role to Level II and 2 lottery entries. That figure is inside the range the employer already advertised.
Based on the DOL prevailing wage for this occupation and worksite, a base salary of $155,896 would place this position at wage Level II. That figure is within the posted range, and I'd like to target it. This role classifies under "Electronics Engineers, Except Computer" for prevailing-wage purposes.
DOL prevailing wage, 2026-27 wage year · Electronics Engineers, Except Computer (17-2072) · San Jose-Sunnyvale-Santa Clara, CA. Wage level is derived by USCIS from the offered wage, occupation and worksite; the occupation shown is inferred from the job title.
Employer immigration record
from this employer's Department of Labor filings
Green-card intent detected
Altera Corporation obtained a prevailing wage determination for Electronics Engineers, Except Computer in San Jose, CALIFORNIA on 2026-06-10. No matching green-card filing appears in our data yet. The determination expires in 2 days (2026-09-07), and a green-card filing must follow before then or the employer starts over.+2 more active determinations on file
Files H-1B transfers
13 transfer filings in the last year, covering 13 workers. Median labor-condition decision: 7 days. An employer that already files transfers is one that can take over an existing H-1B.
Sourced from Department of Labor LCA, PERM and prevailing-wage disclosure data. Employer matching is by name, so figures may be split across an employer's legal entities. Absence of a filing means none appears in our copy of the data, not that none exists.
Community outcomes
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About the role
- At Altera™, our independence as the world's largest pure ‑ play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise.
- Contribute to the development of new FPGA capabilities and improved programmable logic architectures that enable faster and more efficient integration of Altera FPGAs into larger systems.
- The pay range below is for Bay Area California only.
Responsibilities
- Design and develop complex FPGA circuits and IP, including FPGA core fabric logic, interconnect and routing, clocking, configuration, configurable memory blocks, and Network-on-Chip (NoC) architectures.
- Lead microarchitecture definition and perform circuit and logic design for complex FPGA blocks and subsystems, making technical tradeoffs to optimize power, performance, area, timing, reliability, and yield.
- Develop schematics, RTL implementations, behavioral models, and simulations to evaluate and validate new FPGA circuit architectures and capabilities.
- Perform functional and reliability verification of FPGA circuits and IP, working closely with verification teams to identify, debug, and resolve complex design issues.
- Analyze design results and drive improvements to meet aggressive power, performance, area (PPA), timing, reliability, and yield objectives.
- Work closely with microarchitecture, SoC/full-chip, IP fabric and interconnect, RTL design, verification, physical design, and other cross-functional teams to integrate FPGA circuits and IP into larger systems.
- Drive technical resolution of complex design, integration, simulation, timing, and functional issues across multiple engineering disciplines.
- Lead or contribute to design methodology and flow improvements that increase design quality, development efficiency, and scalability across FPGA product generations.
- Provide technical guidance and mentorship to less-experienced engineers and serve as a technical resource for complex FPGA circuit and IP design challenges.
- Support silicon bring-up and post-silicon debug as needed by investigating hardware issues, validating design functionality, and applying lessons learned to future FPGA designs.
Requirements
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, Physics, Math, or a related field and 8+ years of industry experience in FPGA or ASIC design.
- 8+ years of experience in FPGA circuit, IP, or RTL design, including development of complex digital logic, programmable logic, or silicon subsystems.
- 8+ years of experience using industry-standard FPGA or ASIC design tools and flows, including simulation, synthesis, static timing analysis (STA), linting, design-rule or electrical-rule checking, and power analysis.
- 8+ years of experience developing or analyzing timing, power, performance, area, reliability, or yield characteristics of FPGA or ASIC circuits and IP.
- 8+ years of experience developing design models, specifications, or technical collateral used to integrate FPGA circuits or IP into larger hardware and software systems.
- 8+ years of experience independently driving complex technical assignments, resolving design and integration issues, and influencing technical decisions across multiple engineering disciplines.
- We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.
- Applicants must be eligible for any required U.S. export authorizations.
- 8+ years of experience in microarchitecture and logic design for complex digital systems, including experience with FPGA fabric, interconnects, routing, clocking, configuration, memory structures, processor subsystems, or Network-on-Chip (NoC) architectures.
- 8+ years of experience with hardware design and simulation methodologies, including schematic entry, RTL development, behavioral modeling, circuit simulation, functional verification, or related front-end design methodologies.
- 8+ years of experience collaborating with cross-functional engineering teams, including microarchitecture, SoC/full-chip, IP, interconnect/fabric, RTL design, verification, physical design, and/or silicon validation teams.
Nice to have
- 8+ years of experience specifically designing or implementing FPGA routing, interconnect, or programmable fabric architectures.
- 8+ years of experience with FPGA core fabric logic, configurable memory blocks, clocking architectures, configuration logic, or Network-on-Chip (NoC) architectures.
- 8+ years of experience developing FPGA circuit models, timing models, power models, behavioral models, electrical-rule checking methodologies, or other design collateral.
- 8+ years of experience contributing to FPGA or ASIC silicon development through design, verification, integration, tape-out, silicon bring-up, or post-silicon validation.
- 8+ years of experience working across hardware and software interfaces to enable integration of FPGA circuits and IP into larger SoC or system architectures.
- Demonstrated experience mentoring engineers and providing technical leadership on complex FPGA circuit, IP, or architecture challenges.
- Shift 1 (United States of America)
- San Jose, California, United States
Skills
- About Altera
- Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc.
Compensation
- The pay range below is for Bay Area California only.
- Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc.
- We also offer incentive opportunities that reward employees based on individual and company performance.
- $149,100 - $215,000 USD
This listing is sourced directly from Altera's careers page and normalized into a canonical job model.