Astera Labs Inc.
Principal Verification Engineer
San Jose, California, United States · Principal
Stay score
odds of building a lasting career here
Sponsors, but it's cap-subject — you still face the weighted lottery (~61% per draw at Level IV). Good if you win; have a cap-exempt backup on your list.
Lottery odds assume a STEM candidate.
Personalize to your clock →H-1B wage level
the lottery is wage-weighted — each level is one more entry
$2,408 more — $187,408 — moves this role to Level III and 3 lottery entries. That figure is inside the range the employer already advertised.
Based on the DOL prevailing wage for this occupation and worksite, a base salary of $187,408 would place this position at wage Level III. That figure is within the posted range, and I'd like to target it. This role classifies under "Electronics Engineers, Except Computer" for prevailing-wage purposes.
DOL prevailing wage, 2026-27 wage year · Electronics Engineers, Except Computer (17-2072) · San Jose-Sunnyvale-Santa Clara, CA. Wage level is derived by USCIS from the offered wage, occupation and worksite; the occupation shown is inferred from the job title.
Employer immigration record
from this employer's Department of Labor filings
Files H-1B transfers
Sourced from Department of Labor LCA, PERM and prevailing-wage disclosure data. Employer matching is by name, so figures may be split across an employer's legal entities. Absence of a filing means none appears in our copy of the data, not that none exists.
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About the role
- Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions.
Responsibilities
- Collaborate closely with software and system validation teams to create and execute test plans on emulation platforms.
- Work with RTL designers to troubleshoot and resolve design issues.
- Drive verification strategy and methodology for SoCs in server and networking applications.
Requirements
- Familiarity with verification of switching architectures, including packet processing and forwarding engines.
- Excellent communication skills and ability to work independently with minimal supervision.
Nice to have
- Experience with third-party Verification IP for protocols such as PCIe, Ethernet, and InfiniBand.
- Background in Network-on-Chip (NoC) architectures for smart NICs and AI accelerators.
- Knowledge of Ethernet/PCIe switching and central buffer architectures.
- Experience with emulation platforms and hardware-software co-verification
- Apply both directed and constrained-random verification techniques using SystemVerilog/UVM and other relevant tools.
- Bachelor's degree in Electrical Engineering (Master's preferred).
- 8+ years of experience in SoC verification, particularly for server and networking applications.
- Expertise in SystemVerilog/UVM and hands-on experience across the full verification lifecycle.
Compensation
- Salary range is $185,000 to $230,000 depending on experience, level, and business need.
Benefits
- Lead the functional verification of advanced ASICs, including test planning, development, execution, and coverage analysis.
- Debug test failures, analyze coverage results, and close functional coverage gaps to ensure comprehensive verification.
This listing is sourced directly from Astera Labs Inc.'s careers page and normalized into a canonical job model.