Phizenix

Phizenix

Staff DFT Engineer

Santa Clara, CA (Onsite) · Staff+

Sponsorship not specified$130k-$180kDetected 78 days ago
Electrical EngineeringCommunicationProblem SolvingMentoring

About the role

  • This role focuses on end-to-end scan execution, from insertion and verification through DRC closure, coverage improvement, and final DFT signoff.

Responsibilities

  • Lead hands-on scan DFT implementation, including:Scan insertion and stitching
  • Perform scan DFT verification, debug, and DFT DRC closure
  • Run, analyze, and debug SpyGlass DFT/RTL checks, partnering with design teams to resolve violations
  • Develop and validate DFT-related timing constraints (scan, shift, capture, and test modes)
  • Optimize scan implementations for pattern efficiency and test quality
  • Support hierarchical scan integration at both block and SoC levels
  • Collaborate closely with RTL and Physical Design teams to resolve scan-related issues
  • Support pre-silicon DFT signoff and post-silicon pattern bring-up and debug

Requirements

  • Bachelor's degree in Computer Science, Electrical Engineering or
  • related fields and 5-10 years of related professional experience OR Master's degree and/or PhD in Computer Science, Electrical Engineering or
  • related fields with 3-5 years of experience.
  • 8+ years of hands-on experience in DFT scan implementation
  • Strong expertise with Siemens Tessent, including:Scan insertion and verification
  • Strong understanding of:Scan Streaming Network (SSN)
  • What You Can Expect

Nice to have

  • Experience with scan compression and advanced scan architectures
  • Post-silicon experience, including:Pattern bring-up and debug
  • Experience mentoring junior engineers or owning DFT scan signoff

Compensation

  • California Pay Range

Benefits

  • Analyze ATPG results and drive scan coverage improvement and closure
  • Create and maintain TCL scripts for scan insertion, ATPG setup, and coverage analysis
  • The ideal candidate will own scan quality, coverage closure, and DFT signoff for complex SoC designs.

Company info

  • We are looking for a Senior Staff DFT Engineer with hands-on experience in scan-based DFT implementation, including Scan Streaming Network (SSN) and IJTAG (IEEE 1687).
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This listing is sourced directly from Phizenix's careers page and normalized into a canonical job model.