Lightmatter

Sr. Staff Physical Design Timing Engineer (STA)

Toronto, ON · Staff+ · Full-time

Sponsorship not specified$191k-$220kDetected 5 days ago

PythonValuationCadenceElectrical EngineeringCommunicationProblem Solving

About the role

You will work alongside a team of world-class scientists and engineers in defining how the system will be optimized and trailblaze problems that are new to the industry.
If your passion is innovation, solving challenging technical problems and doing impactful work you should join our team.
In this job you will be responsible for timing constraints development, STA and timing closure on leading edge CMOS technologies and flows.

Drive the STA sign-off for our flagship Silicon photonics chips at various technology nodes.
Collaborate with the architecture, RTL, and DFT teams to analyze the timing complexities and develop consolidated timing modes and constraints for synthesis, along with PnR and chip timing sign-off flows.
Analyze and understand the tradeoffs between power/performance and area goals to drive them into overall chip implementation flows.
Leverage Tempus/PrimeTime to automate timing ECO generation for effective closure and support physical design implementation.
Document best practices and lessons learned to drive continuous improvements in future projects.

Bachelor's degree in Electrical Engineering or Computer engineering
12 years of Physical Design experience, with a minimum of 5 years hands-on experience in ASIC STA and timing constraints development, timing closure with Cadence or Synopsys tools
Experience in driving timing closure by effectively managing on-chip variation derates, optimizing multi-mode multi-corner constraints, and implementing robust clock tree building strategies
Well versed with scripting languages like TCL and Python, PERL, or Shell
Strong problem solving skills with attention to every technical aspect
Be a strong team player with clear and precise communication skills
Preferred Qualifications:
We offer competitive compensation. The base salary range for this role determined based on location, experience, educational background, and market data.

Master's degree in Electrical Engineering or Computer engineering
A minimum of 8 years of hands-on experience in ASIC STA and timing constraints development, timing closure with Cadence or Synopsys tools

Lightmatter is leading the revolution in AI data center infrastructure, enabling the next giant leaps in human progress.
Lightmatter raised $400 million in its Series D round, reaching a valuation of $4.4 billion.
Lightmatter is (re)inventing the future of computing with light!
This includes synthesis through place and route, timing closure, and tapeout signoff.

total compensation goes beyond base salary, it also includes a new hire equity grant, annual performance-based equity, and other rewards that recognize your impact and contribution.
$191,000 - $220,000 CAD

Comprehensive Health Care Plan (Medical, Dental & Vision)
Retirement Savings Matching Program
Life Insurance (Basic, Voluntary & AD&D)
Generous Time Off (Vacation, Sick & Public Holidays)
Paid Family Leave
Short Term & Long Term Disability
Commuter Benefits
Equity grants (applicable to full-time employees)
Lightmatter recruits, employs, trains, compensates, and promotes regardless of race, religion, color, national origin, sex, disability, age, veteran status, and other protected status as required by applicable law.
Flexible, hybrid workplace model

We are hiring a Physical Design Timing Engineer to help drive backend digital execution for some of the leading photonics based interconnect solutions.

This listing is sourced directly from Lightmatter's careers page and normalized into a canonical job model.