Altera
Senior Physical Design Engineer
San Jose, California, United States · Senior
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odds of building a lasting career here
Sponsors, but it's cap-subject — you still face the weighted lottery (~61% per draw at Level IV). Good if you win; have a cap-exempt backup on your list.
Lottery odds assume a STEM candidate.
Personalize to your clock →H-1B wage level
the lottery is wage-weighted — each level is one more entry
$22,696 more — $155,896 — moves this role to Level II and 2 lottery entries. That figure is inside the range the employer already advertised.
Based on the DOL prevailing wage for this occupation and worksite, a base salary of $155,896 would place this position at wage Level II. That figure is within the posted range, and I'd like to target it. This role classifies under "Electronics Engineers, Except Computer" for prevailing-wage purposes.
DOL prevailing wage, 2026-27 wage year · Electronics Engineers, Except Computer (17-2072) · San Jose-Sunnyvale-Santa Clara, CA. Wage level is derived by USCIS from the offered wage, occupation and worksite; the occupation shown is inferred from the job title.
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Green-card intent detected
Files H-1B transfers
Sourced from Department of Labor LCA, PERM and prevailing-wage disclosure data. Employer matching is by name, so figures may be split across an employer's legal entities. Absence of a filing means none appears in our copy of the data, not that none exists.
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About the role
- At Altera™, our independence as the world's largest pure ‑ play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise.
- Strong analytical and problem-solving skills with the ability to debug complex physical implementation challenges.
Responsibilities
- Perform physical design implementation of custom IP and SoC designs from RTL through GDSII to create a manufacturing-ready design database.
- Execute all aspects of the physical design flow, including synthesis, floorplanning, place and route, clock tree synthesis (CTS), static timing analysis (STA), power and clock distribution, reliability analysis, and power/noise analysis.
- Perform physical verification and design signoff, including formal equivalence checking, static timing verification, reliability verification, power integrity analysis, layout verification, electrical rule checking (ERC), and structural design checking.
- Analyze implementation and signoff results, identify violations, and develop solutions that improve current and future product architectures.
- Optimize physical designs to improve power, performance, frequency, and area (PPA).
- Collaborate with cross-functional engineering teams to resolve implementation challenges throughout the design cycle.
- Participate in the development and continuous improvement of physical design methodologies, design flows, and automation.
- Ability to manage multiple technical priorities in a fast-paced development environment.
- Passion for delivering high-quality silicon and continuously improving design methodologies.
- As an independent company, we move faster, invest deeper, and partner more closely-empowering our teams to drive breakthrough innovation and shape the future of the FPGA industry.
Requirements
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline.
- 6+ years of hands-on experience with digital ASIC or SoC physical design implementation.
- 6+ years of experience performing RTL-to-GDSII physical design flows.
- 6+ years of experience with synthesis, floorplanning, place and route, and clock tree synthesis (CTS).
- 6+ years of experience performing static timing analysis (STA) and timing closure.
- 4+ years of experience with physical verification, including DRC, LVS, ERC, and signoff methodologies.
- 4+ years of experience using industry-standard physical design EDA tools such as Synopsys Fusion Compiler, ICC2, PrimeTime, Cadence Innovus, or equivalent.
- 3+ years of experience optimizing designs for power, performance, and area (PPA).
- 2+ years of experience supporting designs with multiple voltage or power domains.
- We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.
Nice to have
- Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
- Experience with advanced semiconductor process nodes (7nm, 5nm, 3nm, or similar).
- Experience with physical design automation, scripting, and methodology development using Python, Tcl, Perl, or Shell.
- Experience working on large-scale SoC or FPGA architectures.
- Familiarity with power integrity, IR drop, electromigration (EM), and signal integrity analysis.
- Experience collaborating across architecture, RTL, timing, DFT, verification, and CAD teams in a high-volume product development environment.
- Shift 1 (United States of America)
- San Jose, California, United States
Skills
- About Altera
- Excellent collaboration and communication skills within cross-functional engineering teams.
- Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc.
Compensation
- The pay range below is for Bay Area California only.
- Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc.
- We also offer incentive opportunities that reward employees based on individual and company performance.
- $133,200 - $192,825 USD
Company info
- We also offer incentive opportunities that reward employees based on individual and company performance.
This listing is sourced directly from Altera's careers page and normalized into a canonical job model.