Lumilens

Lumilens

Sr. Physical Design Engineer

San Jose · Senior

Sponsorship not specifiedDetected 12 days ago
PythonNode.jsCloud PlatformsCadenceElectrical EngineeringSignal Processing

About the role

  • We are seeking a Senior Physical Design Engineer to join our silicon design team developing high-performance ASIC using TSMC advance process nodes, including 5nm and 3nm.
  • In this role, you will own physical implementation from RTL to GDSII, drive timing and power closure for ultra-high-speed designs, and work closely with RTL, STA, IP, and verification teams to solve complex implementation challenges unique to advanced-node and high-speed transceiver architectures.

Responsibilities

  • Physical Implementation: Own full-chip and block-level physical implementation, including floorplanning, placement, CTS, routing, and physical verification for high-speed designs in advanced TSMC nodes.
  • Timing, Power, and Area Closure: Collaborate closely with RTL and STA teams to ensure clean handoffs and convergent timing, area, and power closure across complex design blocks and full chip.
  • Advanced Physical Design: Apply physical design techniques for multi-voltage and multi-frequency domains, hierarchical implementation, physical-aware synthesis, congestion mitigation, skew optimization, and RC extraction-aware placement and routing.
  • Signoff and Tape out: Perform tapeout signoff activities, including PV, EM/IR, ESD and ejobview using industry-standard verification tools.
  • Own full-chip and block-level physical implementation, including floorplanning, placement, CTS, routing, and physical verification for high-speed designs in advanced TSMC nodes.
  • Collaborate closely with RTL and STA teams to ensure clean handoffs and convergent timing, area, and power closure across complex design blocks and full chip.
  • Apply physical design techniques for multi-voltage and multi-frequency domains, hierarchical implementation, physical-aware synthesis, congestion mitigation, skew optimization, and RC extraction-aware placement and routing.
  • 8+ years of hands-on physical design experience, preferably with advanced technology nodes at 5nm or below.
  • Professional development opportunities and certification support

Requirements

  • Physical Design Expertise: Strong experience with floorplanning, placement, CTS, routing, IR drop mitigation, timing closure, and signoff debugging.
  • Tools and Automation: Hands-on experience with tools such as Synopsys ICC2, RedHawk SC, Cadence Innovus, Voltus, Simens Calibre etc, along with strong scripting skills in Tcl, Python, or Perl.
  • High-Speed PHY Implementation: Experience with high-speed PHY such as SerDes, UCIe etc physical design implementation.
  • Education: Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or a related field.
  • Advanced-Node Signoff: Familiarity with EM/IR analysis, power grid optimization, congestion analysis, physical verification, and tapeout signoff in advanced semiconductor process nodes.
  • High-Frequency Design Exposure: Experience supporting high-frequency datapath or DSP-heavy designs is a plus.

Nice to have

  • 2.5D or 3D design experience: Experience with TSMC CoWoS or SoIC-X design experience is a strong plus.

Skills

  • Preferred Qualifications (Bonus)
  • We're a well-funded startup backed by Mayfield and led by veterans who've built
  • And scaled some of the most transformative technologies in the industry.
  • incremental innovation, it's a ground-floor opportunity to rethink the optical layer from
  • the silicon up.
  • You'll work alongside a team of world-class engineers solving some of
  • the hardest challenges in optics, systems, and scale.
  • Every line of code, every design
  • If you're looking for mission, momentum, and the chance to make an outsized impact
  • jump on the rocket ship.

Compensation

  • Competitive salary commensurate with experience

Benefits

  • Comprehensive benefits package including health insurance
  • All qualified applicants will receive consideration without regard to race, color, religion, gender, identity, orientation, veteran status, disability, or any other legally protected status.

Equal opportunity

  • equal opportunity employer.
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