Nuvacore
CPU Design & Verification Engineer — New College Grad
Austin, TX · Internship
Stay score
odds of building a lasting career here
Sponsors, but it's cap-subject — you still face the weighted lottery (~61% per draw at Level IV). Good if you win; have a cap-exempt backup on your list.
Lottery odds assume a STEM candidate.
Personalize to your clock →H-1B wage level
the lottery is wage-weighted — each level is one more entry
$12,360 more — $152,360 — moves this role to Level III and 3 lottery entries. That figure is inside the range the employer already advertised.
Based on the DOL prevailing wage for this occupation and worksite, a base salary of $152,360 would place this position at wage Level III. That figure is within the posted range, and I'd like to target it. This role classifies under "Electronics Engineers, Except Computer" for prevailing-wage purposes.
DOL prevailing wage, 2026-27 wage year · Electronics Engineers, Except Computer (17-2072) · Austin-Round Rock-San Marcos, TX. Wage level is derived by USCIS from the offered wage, occupation and worksite; the occupation shown is inferred from the job title.
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from this employer's Department of Labor filings
Files H-1B transfers
Sourced from Department of Labor LCA, PERM and prevailing-wage disclosure data. Employer matching is by name, so figures may be split across an employer's legal entities. Absence of a filing means none appears in our copy of the data, not that none exists.
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About the role
- Write and debug directed and random tests in assembly, C, or random instruction sequences (RIS) to expose corner cases such as speculation, hazards, flushes, and retirement ordering.
- Contribute to functional coverage monitors and help analyze metrics toward test plan closure.
- Assist in performance exploration and correlation, working with performance architecture and verification teams.
Responsibilities
- Nuvacore is building a ground-up, high-performance, low-power CPU for next-generation compute workloads.
- You'll work shoulder-to-shoulder with architects, RTL designers, and verification engineers across units including fetch, decode/rename, scalar execute, fp/vector execute, load/store, memory management/TLB, prefetching, debug/trace, system/IO, and the multi-level cache subsystem - helping build and prove out a CPU that targets industry-leading power, performance, and area.
- Partner with architects to correlate RTL against performance models and help identify throughput, stall, and branch-prediction issues.
- Work with architecture and RTL teams to root-cause failures and support emulation, FPGA, and silicon bring-up.
- Develop and refine RTL targeting power, performance, area, and timing goals.
- Support verification efforts including testbench development, formal methods, and simulation/emulation.
- Collaborate with the physical design team to help meet timing, power, area, DFT, and reliability goals.
- RTL / Micro-Architecture Design
- Internship or project experience in CPU/complex digital design, verification, or RTL development.
Requirements
- BS or MS in Electrical/Computer Engineering, Computer Science, or equivalent practical experience (recent or upcoming graduate).
- Coursework or project experience in digital logic and computer architecture - pipelines, out-of-order execution, branch prediction, or similar topics.
- Experience with assembly-level programming or writing tests in assembly.
Nice to have
- Proficiency in C/C++, SystemVerilog, and/or Verilog, plus familiarity with a scripting language (Python preferred
Compensation
- $140k-$200k
Benefits
- Help build test plans, environments, stimulus generators, checkers, transactors, and coverage that exercise the CPU pipeline end to end.
- Exposure to functional verification concepts (testbenches, checkers, coverage) or RTL design/coding, through coursework, internships, or personal projects.
Company info
- We are seeking new college graduates to join our CPU team, contributing to either Design Verification (DV) or RTL/micro-architecture design.
This listing is sourced directly from Nuvacore's careers page and normalized into a canonical job model.