Microsoft
Senior Physical Design Engineer
Hillsboro, OR, US · Senior
Stay score
odds of building a lasting career here
Thin sponsorship signal and lottery-bound. A low-probability bet with your clock running. Prioritize cap-exempt roles and proven entry-level sponsors first.
Lottery odds assume a STEM candidate.
Personalize to your clock →Employer immigration record
from this employer's Department of Labor filings
Green-card filing pattern in this occupation
Green-card follow-through: 87%
Reported a layoff in this occupation
Files H-1B transfers
Sourced from Department of Labor LCA, PERM and prevailing-wage disclosure data. Employer matching is by name, so figures may be split across an employer's legal entities. Absence of a filing means none appears in our copy of the data, not that none exists.
Community outcomes
No reports yet — be the first to help the next applicant.
About the role
- Responsible for clock construction and CTS.
- Clear communications on project status & planning.
- To meet this legal requirement, and as a condition of employment, the successful candidate's citizenship will be verified with a valid passport.
Responsibilities
- Drive end-to-end execution from synthesis through place-and-route for large designs, ensuring completion of all signoff stages including timing, physical verification, EMIR, formal equivalence, and low-power verification.
- Drive methodology exploration activities to optimize SOC blocks for clock construction and related methodology.
- Coordinate with CAD, RTL/Design teams/DFT, Architecture team, Power & Performance team, Technology team & other internal/external partners as essential.
- Responsible for RTL to GDS implementation in Physical Design domain.
- Influence design tools, flows, and methodologies in construction, signoff, and optimization through a data-driven approach.
- Demonstrate technical expertise across various domains of Physical Design.
- Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.
- Proven track record in Physical Design domain implementing designs through synthesis, floorplanning, place and route, extraction, timing, and physical verification.
- Experience in low power design methodology for SOC Thorough understanding of SOC or subsystem design trade-offs across power, performance, and area (PPA).
- Familiarity with various clock construction strategies for high speed designs Demonstrate technical expertise in all aspects of Physical Design, from synthesis to place and route of partitions through all signoff including timing signoff, physical verification, EMIR signoff, Formal Equivalence, and Low Power Verification.
Requirements
- BS/MS in Electrical or Computer Engineering or any related degree Min 7+ years of experience in semiconductor design.
- Communication, collaboration and teamwork skills and ability to contribute to diverse and inclusive teams.
- Production silicon tape-outs experience in advanced foundry process nodes.
Visa & Work Authorization
- This role will require access to information that is controlled for export under export control regulations, potentially under the U
This listing is sourced directly from Microsoft's careers page and normalized into a canonical job model.