Cientra
Design Verification Engineer
San Francisco, CA, United States
Sponsorship not specifiedDetected 1785 days ago
PythonC++Object-Oriented ProgrammingData StructuresAlgorithmsVerilogCommunication
About the role
- Additional Information All your information will be kept confidential according to EEO guidelines.
Responsibilities
- As a Design Verification Engineer you will contribute to the functional verification of GPU Subsystems such as Shader, Texture, and Memory Systems.
- Maintain efficient and clean regression status
- Develop Scalable SystemVerilog/UVM testbenches for unit level and/or Cluster level verification.
- Define, maintain and execute unit level and/or Cluster level verification testplans.
- 5-15 year's industry experience in a design verification role.
- Understanding of micro-architecture, logic design, FSMs, arithmetic datapath pipelines.
Nice to have
- Knowledge of GPU, experience with Shader, Texture, or Memory System a plus
- Proficient in System Verilog/UVM/OVM, OOP/C++
- Experience in creating, running and debugging of SystemVerilog/UVM constraint-random Testbench.
- Excellent working knowledge of scripting languages such as Python or Perl.
- Strong debugging skills
- Strong programming skills with good understanding of algorithms and data structures
- Good verbal and written communication skills.
Benefits
- Code Functional coverage models and System Verilog assertions.
- Drive Functional Coverage and Code coverage to closure.
- Experience with code coverage and functional coverage driven verification methodology.
- Strong functional verification experience including Test planning, Testbench Architecture, Test/Coverage Model/Assertion Development.
Equal opportunity
- All your information will be kept confidential according to EEO guidelines.
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This listing is sourced directly from Cientra's careers page and normalized into a canonical job model.