Astera Labs Inc.
Principal Post-Silicon Validation Engineer
San Jose, California, United States · Principal
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odds of building a lasting career here
Sponsors, but it's cap-subject — you still face the weighted lottery (~61% per draw at Level IV). Good if you win; have a cap-exempt backup on your list.
Lottery odds assume a STEM candidate.
Personalize to your clock →H-1B wage level
the lottery is wage-weighted — each level is one more entry
$11,899 more — $218,899 — moves this role to Level IV and 4 lottery entries. That figure is inside the range the employer already advertised.
Based on the DOL prevailing wage for this occupation and worksite, a base salary of $218,899 would place this position at wage Level IV. That figure is within the posted range, and I'd like to target it. This role classifies under "Electronics Engineers, Except Computer" for prevailing-wage purposes.
DOL prevailing wage, 2026-27 wage year · Electronics Engineers, Except Computer (17-2072) · San Jose-Sunnyvale-Santa Clara, CA. Wage level is derived by USCIS from the offered wage, occupation and worksite; the occupation shown is inferred from the job title.
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Sourced from Department of Labor LCA, PERM and prevailing-wage disclosure data. Employer matching is by name, so figures may be split across an employer's legal entities. Absence of a filing means none appears in our copy of the data, not that none exists.
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About the role
- Astera Labs is looking for a Principal Post-Silicon Validation Engineer to take our connectivity silicon from first-silicon bring-up to production-ready.
- Your work will directly shape the quality, performance, and time-to-market of the products that connect the world's most advanced AI platforms, in a hyper-growth company where your technical judgment carries real weight.
Responsibilities
- Architect and drive end-to-end post-silicon validation plans, from first-silicon bring-up through characterization and production release
- Lead lab bring-up of new silicon, including board, firmware, and software readiness
- Partner with design and DFT teams to feed findings back into current and future product generations
- Develop scalable validation automation frameworks and test content using Python and C/C++
- Build and improve lab infrastructure, test benches, and data analysis flows to increase validation throughput
Requirements
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field
- 8-12 years of experience in post-silicon validation, silicon bring-up, or hardware characterization
- Hands-on experience with high-speed serial interfaces such as PCIe, including a strong understanding of the physical layer
- Proficiency in lab equipment, including oscilloscopes, BERTs, protocol analyzers, and power supplies
- Proven ability to debug complex hardware and firmware issues to root cause
Nice to have
- Master's degree or PhD in Electrical Engineering, Computer Engineering, or a related field
- Experience with PCIe Gen 5 or Gen 6, Ethernet, or retimer products
- Experience with SerDes characterization, equalization tuning, and link margining
- Track record of taking multiple products from first silicon to volume production
Skills
- Debug complex silicon, firmware, and system-level failures to root cause across the hardware/software boundary
- Analyze large validation datasets to identify trends, outliers, and risks early
- Mentor engineers and set best practices for validation methodology across the team
Compensation
- Salary range is $207,000 to $230,000 depending on experience, level, and business need.
Benefits
- Define test strategies, coverage goals, and exit criteria in partnership with design, architecture, and product teams
This listing is sourced directly from Astera Labs Inc.'s careers page and normalized into a canonical job model.