Etched
Physical Design Engineer - Flow & Methodologies
San Jose · Senior
Stay score
odds of building a lasting career here
Thin sponsorship signal and lottery-bound. A low-probability bet with your clock running. Prioritize cap-exempt roles and proven entry-level sponsors first.
Lottery odds assume a STEM candidate.
Personalize to your clock →Employer immigration record
from this employer's Department of Labor filings
Files H-1B transfers
Sourced from Department of Labor LCA, PERM and prevailing-wage disclosure data. Employer matching is by name, so figures may be split across an employer's legal entities. Absence of a filing means none appears in our copy of the data, not that none exists.
Community outcomes
No reports yet — be the first to help the next applicant.
About the role
- Etched is building a new category of AI hardware: frontier inference clusters.
- As a Physical Design Methodology Engineer, you will architect our PD flow from first principles.
- You will own the infrastructure that allows our design team to iterate at unprecedented speeds, directly accelerating our time-to-market and enabling PPA gains that aren't possible with off-the-shelf CAD methodologies.
Responsibilities
- Architect, build, and maintain our automated RTL-to-GDSII flow, from synthesis through place and route to signoff handoff.
- Build and own the CAD infrastructure supporting PD, including tool version qualification and deployment, and efficient use of compute and licenses.
- Drive dashboards that show the convergence of projects related to PD, including timing, physical verification, and utilization trends.
- Optimize tool flows and work with EDA vendors to evaluate and incorporate the latest features.
- Define reference flows, QoR targets, and delivery checklists for 3rd party physical design services, and audit deliveries against them.
- Partner with block and top-level owners to debug flow issues and encode fixes into the methodology rather than one-off patches.
- Create block level and full chip level PG mesh from scratch using design rule documents, design requirements, and EM/IR feedback.
- Create and maintain a DRC-clean floorplanning flow and enable floorplan signoff checks.
- Drive PPA tuning to optimize tool settings for best power, performance, and area outcomes.
- Establish and maintain timing correlation from pre-route through post-route and between implementation and signoff tools.
Requirements
- 5-10+ years of previous experience with PD or PD methodology/CAD
- Experience with DRC-clean floorplanning flows and automated checks
- Experience with Cadence (Innovus, Genus) or Synopsys ( Fusion Compiler) automated RTL-to-GDSII flows
- Experience with PPA tuning and timing correlation across pre-route, post-route, and signoff environments
- Experience integrating sign-off tools (PrimeTime, Tempus, Voltus, Pegasus, Calibre) into production flows
- Experience with back-end design on advanced process nodes (5nm and below)
- Experience with UPF-based low power design methodology and multi-mode multi-corner setup
Benefits
- Medical, dental, and vision packages with generous premium coverage
- $500 per month credit for waiving medical benefits
- Various wellness benefits covering fitness, mental health, and more
Company info
- We are the first inference-focused frontier AI system.
- We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills.
This listing is sourced directly from Etched's careers page and normalized into a canonical job model.