Ambarella Corp.
ASIC Design Engineer Intern
US Headquarters · Intern · Internship
Sponsorship not specifiedDetected 32 days ago
C++VerilogCommunication
About the role
- AI Vision Processors For Edge Applications Our solutions make cameras smarter by extracting valuable data from high-resolution video streams.
Responsibilities
- Synthesize and optimize RTL for timing, area and power.
- Developing front-end methodologies and tool flows.
Requirements
- Master's degree in Electrical/Electronics/Computer Engineering with 0-5 years of experience.
- Knowledge of System Verilog, Verilog, and Perl.
- Ability to program scripting languages and the ability to write assembly language programs.
- Knowledge of logic synthesis and timing closer
- Logic design, implementation, and verification using Verilog, System Verilog, and any required programing and scripting languages.
Benefits
- AI Vision Processors For Edge Applications
- Developing unit level and cluster level test-benches, BFMs, random test generators, functional coverage monitors, using System Verilog, UVM, C++, and Perl scripts.
- Developing test plan, random and directed test cases, performing logic verification, and functional coverage analysis.
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