credosemi

credosemi

Senior Digital Design Engineer

San Jose, California · Senior

Sponsorship not specified$140k-$170kDetected 10 days ago
PythonVerilogElectrical EngineeringCollaboration

About the role

  • We're looking for a Senior Digital Design Engineer to lead front-end ASIC design efforts, including architecture, implementation, and verification of complex logic blocks.

Responsibilities

  • Write microarchitecture and/or design specifications.
  • Architect/design, implement, and debug complex logic blocks.
  • Support all front-end integration activities like Lint, CDC, Synthesis, and ECO.
  • Develop functional tests/testbenches and run functional RTL and Gate-Level verification/simulations.
  • Work with other ASIC Design/Verification, DFT and Physical Design Engineers in achieving a successful tape out.
  • Collaborate with Software, Firmware, Applications, and Systems teams to ensure a high-quality product.
  • Bring-up, validate, and debug functional features in the chip.
  • You'll collaborate across design, verification, and physical teams to ensure successful tape-outs, while contributing to microarchitecture specs, IP integration, and chip bring-up.
  • This role combines technical depth with cross-functional teamwork to deliver high-performance digital solutions.

Requirements

  • BS or MS in Electrical Engineering, Computer Engineering, or related field with 5-10 years of experience in digital ASIC design
  • Strong understanding of digital logic design, including synchronous and asynchronous interfaces
  • Proficiency in Verilog/SystemVerilog RTL design
  • Familiarity with UVM methodology
  • Hands-on experience with gate-level simulations, chip bring-up, and validation
  • Knowledge of synthesis and static timing analysis
  • Proficiency in scripting languages such as Python, Tcl, Perl, or Shell

Skills

  • Credo is engineering the future of high-speed connectivity for the AI-driven world.

Compensation

  • The base salary range for this position is $140,000 – $170,000 a year.
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