Neurophos

Neurophos

Staff Analog Layout Engineer

Sunnyvale, California · Staff+ · Full-time

Sponsorship not specifiedDetected 50 days ago
PythonCadenceElectrical Engineering

About the role

  • You will develop and optimize high-performance Analog IPs tailored for TSMC's deep-submicron processes, including N12, N3P, and N2P.
  • You will push the boundaries of Power, Performance, and Area (PPA) while mitigating the impact of Restricted Design Rules (RDRs) and electromigration.
  • San Jose, CA or Hsinchu, Taiwan.

Responsibilities

  • Perform custom IC layout execution of high-speed analog/RF circuits.
  • Optimize layout solutions to meet stringent TSMC manufacturing constraints, DFM rules, and antenna restrictions
  • Deliver IP-level floor planning, power planning, and signal distribution, implementing layout techniques for strict ESD and Latch-up prevention.
  • Execute and debug block-level design sign-offs, including DRC (Design Rule Check), LVS (Layout Versus Schematic), and RC Extraction using standard industry tools.
  • implement the power and clock delivery networks to ensure power and signal integrity.
  • Coordinate directly with circuit designers, CAD engineers, and EDA vendors to ensure IP design fits seamlessly into the production flow.
  • Evaluate layout trade-offs among area, yield, and performance; implement the power and clock delivery networks to ensure power and signal integrity.
  • Instead of traditional electronic circuits, we use silicon photonics and an active, programmable metasurface to perform matrix multiplications at the speed of light.

Requirements

  • B.S. or M.S. degree in Electrical Engineering, Computer Engineering, or a closely related discipline.
  • 3-8+ years of professional custom or block-level IC layout experience in deep-submicron, advanced FinFET/GAA nodes (3nm, 2nm, etc.).
  • Mastery of industry-standard EDA tools for layout and verification (e.g., Cadence Virtuoso, Synopsys Custom Compiler, Mentor Calibre, Siemens ICV).
  • Deep understanding of deep-submicron layout techniques, parasitic reduction, matching strategies, and electro-migration (EM/IR).

Skills

  • Prior tape-out success in TSMC N3 or N2 process nodes.
  • Domain knowledge in laying out high-performance analog/mixed signal blocks, such as PLLs and Data Converters (ADC/DAC).
  • Working knowledge of layout automation scripting languages (e.g., TCL, Perl, Python).

Benefits

  • 100% coverage of base health plan premiums for you and your dependents, plus HSA contributions.
  • Unlimited PTO.
  • No rigid vacation banks, just a focus on delivery.
  • 401(k) matching and stock option opportunities to ensure our success is your success.
  • Full suite of voluntary benefits, including Dental, Vision, Life, Hospital, Critical Illness, and Accident insurance.
  • Personalized Benefits.

Company info

  • Work on game-changing technology at the intersection of photonics and AI as part of a collaborative, brilliant team.
  • At Neurophos, we offer:
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This listing is sourced directly from Neurophos's careers page and normalized into a canonical job model.