d-Matrix

d-Matrix

Staff Analog Design Engineer, SerDes Clocking

Santa Clara · Staff+

Sponsorship not specifiedDetected 63 days ago
PythonMATLABLLMsBudgetingCadenceVerilogElectrical EngineeringSignal Processing

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About the role

  • This is a hands-on, transistor-level analog design role owning the clocking subsystem of d-Matrix's high-speed SerDes on our IO chiplet - including the PLL, DLL, phase interpolator, high-frequency clock distribution, and clock and data recovery (CDR) loop.
  • This block set most often determines whether a link closes, and you will personally carry your designs from specification through silicon characterization.
  • The work spans porting proven clocking blocks to new process nodes and ground-up design for our next-generation link, partnering closely with datapath, DSP, digital, and firmware teams to close timing, jitter budgets, and calibration across the full SerDes macro.

Responsibilities

  • Own transistor-level design of low-jitter frequency synthesis - LC and/or ring PLL, including loop filter, charge pump or digital loop, VCO, and divider chain.
  • Own the phase interpolator and phase rotation scheme, including INL/DNL, glitch behavior, and interpolation resolution against the CDR's needs.
  • Design high-frequency clock distribution across the SerDes macro: buffer chains, duty-cycle correction, quadrature generation and correction, skew control, and supply isolation.
  • Build phase-noise and jitter budgets for the link and own the analysis showing where jitter originates.
  • Drive layout of your blocks in deep sub-micron nodes, with particular attention to inductor and VCO layout, shielding, symmetry, and supply/substrate isolation.
  • BS/MS/PhD in Electrical Engineering, with 5+ years of hands-on analog and mixed-signal circuit design experience.
  • Deep knowledge of PLL architecture, loop dynamics, VCO design, and phase noise theory, along with working knowledge of CDR architectures and the loop analysis behind jitter tolerance and jitter transfer.
  • Circuit design experience in advanced FinFET or GAA process nodes, using industry-standard analog design and simulation tools and methodologies (e.g., Cadence Virtuoso, Spectre, Monte Carlo/corner analysis, post-layout simulation).

Requirements

  • Practical experience with jitter decomposition and budgeting methodology, including quantifying contributors in simulation.
  • Silicon bring-up and bench debug experience with lab equipment such as phase noise analyzers, high-speed scopes, and BERTs.

Nice to have

  • Die-to-die interconnect experience - UCIe, BoW, or a proprietary D2D PHY - including clocking architecture choices specific to short-reach, low-energy-per-bit links.
  • Forwarded-clock and matched-source-synchronous architectures alongside embedded-clock CDR.
  • Experience porting a clocking block across process nodes, with a realistic sense of what that effort costs.
  • Participation in or contribution to standards bodies.

Company info

  • At d-Matrix, we are focused on unleashing the potential of generative AI to power the transformation of technology.
  • We are at the forefront of software and hardware innovation, pushing the boundaries of what is possible.
  • Our culture is one of respect and collaboration.
  • We value humility and believe in direct communication.
  • Our team is inclusive, and our differing perspectives allow for better solutions.
  • We are seeking individuals passionate about tackling challenges and are driven by execution.
  • Ready to come find your playground?
  • Together, we can help shape the endless possibilities of AI.

Equal opportunity

  • Employment Policy
  • d-Matrix is proud to be an equal opportunity workplace and affirmative action employer. We're committed to fostering an inclusive environment where everyone feels welcomed and empowered to do their best work. We hire the best talent for our teams, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status. Our focus is on hiring teammates with humble expertise, kindness, dedication and a willingness to embrace challenges and learn together every day.
  • d-Matrix does not accept resumes or candidate submissions from external agencies. We appreciate the interest and effort of recruitment firms, but we kindly request that individual interested in opportunities with d-Matrix apply directly through our official channels. This approach allows us to streamline our hiring processes and maintain a consistent and fair evaluation of al applicants. Thank you for your understanding and cooperation.
  • d-Matrix is proud to be an equal opportunity workplace and affirmative action employer.
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