Logos Space

Logos Space

Senior FPGA Modem Engineer

Mountain View, CA · Senior · Contract

Sponsorship not specifiedDetected 2 days ago
C++GitLinuxFPGAVHDLVerilogEmbedded SystemsElectrical EngineeringHardware DesignSignal Processing5G/LTELeadershipCommunication

About the role

  • You will work closely with the modem systems team on realization of waveform designs using fixed-point FPGA digital hardware and DSP blocks.
  • The Baseband Modem hardware team at Logos Space is building a high-performance digital modem payload for the Logos LEO satellite system that supports high-throughput, secure, reliable and resilient communications with an emphasis on waveform flexibility using Software Defined Radio (SDR) technology.
  • We are looking for digital FPGA hardware engineers who can work well in a fast-paced environment, turn sometimes ambiguous requirements into practical hardware implementations, and collaborate closely with adjacent teams.

Responsibilities

  • Own one or more FPGA-based modem chains through all development phases, from micro-architecture through to lab deployment.
  • Define the micro-architecture of high-rate FPGA modem blocks and surrounding digital infrastructure. Implement designs using SystemVerilog or Verilog.
  • Develop block-level and end-to-end self-checking hardware verification environments using golden reference models provided by the modem systems team.
  • Define and implement clean hardware/software interfaces, including registers, configuration, telemetry, fault and status signaling, and test hooks.
  • Conduct code and design reviews and participate in multi-functional reviews.
  • Collaborate with systems architects, HW engineering design teams and FW/SW design teams for lab bring-up of boards combining FPGA, firmware, RF, and Networking functions.
  • As a Senior FPGA Modem Engineer, you will design, implement, verify and release FPGA-based modem solutions for end-to-end wireless satellite communications links.
  • This role is an exciting opportunity to help build a LEO satellite communications system from the ground up using cutting-edge FPGA technology.

Requirements

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related STEM field.
  • Proficiency in one or more HDL programming languages such as VHDL, Verilog, or SystemVerilog.
  • Experience writing verification frameworks using SystemVerilog/UVM, Cocotb or transactional-level modeling.
  • Experience with industry-standard bus interfaces such as AXI and AXI-streaming and high-speed interfaces such as DDR4/5, 10/40/100 Gb Ethernet and SERDES interfaces like JESD-204B/C, Aurora and Interlaken.
  • Experience with FPGA toolchains and workflows such as AMD Vivado, including simulation, synthesis, place-and-route, timing analysis and closure as well as power analysis.
  • Experience debugging FPGA or digital hardware in the lab using oscilloscopes, logic analyzers, spectrum analyzers, time-interval measurement tools, or similar instrumentation.
  • Familiarity with Linux-based development environments, Git, and automated testing.
  • Ability to prioritize work, complete multiple tasks and work under deadlines with minimal supervision.
  • Employment offers are contingent on the candidate's ability to access export-controlled information in accordance with U.S. law.
  • Analyze results and implement design changes required to close timing and meet system-level FPGA power and resource requirements.

Nice to have

  • Experience implementing both the MAC and PHY layers of a wireless modem such as 5G OFDMA or Single-Carrier DVB-S2(X) through the entire product life cycle for an FPGA or ASIC target.
  • Experience with space, defense, or other reliability-critical electronics, including radiation-tolerant design, Triple Modular Redundancy (TMR), and single-event upset (SEU) mitigation techniques.
  • Experience with embedded firmware or low-level software for device control, board bring-up, telemetry, and calibration workflows.
  • Experience with board-level digital or mixed-signal hardware design, schematic review, clock-tree or oscillator circuitry and hardware bring-up.
  • Experience writing tests and automation scripts using C, C++ or Python.
  • Experience designing HW accelerators tightly coupled with the embedded processor subsystems present in most modern FPGA devices.
  • Experience with the architecture, toolchains and programming of SIMD vector DSP engines for wireless modem applications.
  • Even if you don't meet every qualification, we encourage you to apply.

Skills

  • Speed and reliability are the foundation of the system.
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This listing is sourced directly from Logos Space's careers page and normalized into a canonical job model.