Astera Labs Inc.
STA Physical Design Engineer, Senior Principal
San Jose, California, United States · Principal
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About the role
- Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions.
- This role is fully on-site and in-person.
- The base salary range is USD 207,000.00 USD - USD 230,000.00.
Responsibilities
- Independently drive PnR activities from RTL to GDS, ensuring robust signoff across complex SoCs or sub-systems.
- A good understanding of SDC constraints, be able to interact with design team on constraints refinement.
- Work with top level owners on defining and managing I/O timing budgets across hierarchical designs.
- Knowledge of different ways to build hierarchical design (black-box model, ETM or abstract model etc).
- Partner closely with design, implementation, and verification teams to drive block/top convergence, providing sign-off level expertise and guidance.
Requirements
- ≥10 years of experience in PnR and sign-off for complex SoCs in Server, Storage, or Networking applications.
- Expertise in PnR, Extraction, Timing closure, EM-IR, Formality and DRC/LVS at both block and full-chip level.
- Strong knowledge of synthesis, place-and-route, extraction, and equivalence checking flows in advanced nodes (7nm or below).
- Proficiency with Cadence and/or Synopsys physical design/STA toolchains.
- Ability to work independently with strong prioritization and a professional, customer-focused mindset.
- Familiarity with high-speed SERDES and Ethernet PHY timing challenges.
- Experience working with IP vendors for both RTL and hard-macro integration.
Nice to have
- Master's preferred.
- Preferred Experience
- Bachelor's in Electrical Engineering or Computer Science required
Compensation
- The base salary range is USD 207,000.00 USD - USD 230,000.00.
This listing is sourced directly from Astera Labs Inc.'s careers page and normalized into a canonical job model.