Hpe

Hpe

AIML enhanced Design/Verification Methodology Engineer

Sunnyvale, California, United States of America

Sponsorship not specified$81k-$164kDetected 12 hours ago
PythonCadenceFPGAVerilogElectrical EngineeringCommunicationCollaboration

About the role

  • We know varied backgrounds are valued and succeed here.
  • We make bold moves, together, and are a force for good.
  • These includes but not limited to: - Creat ing UVM-based testbench environments from ground up or enhance the existing ones.

Responsibilities

  • Use both "classical" and Generative-AI methodologies to a rchitect, develop, and maintain agents, skills, and other AI based infra-structures.
  • The ideal person will have balanced knowledge of chip design and AIML methodologies to contribute meaningfully to the creation of architecture, design, verification, and physical design assets.
  • AIML enhanced Design/Verification Methodology Engineer
  • Any reliance on fraudulent communication is at the individual's own risk, and HPE disclaims legal liability for any resulting damages.
  • We have the flexibility to manage our work and personal needs.
  • Perform ing root cause analysis of failures and work with design teams to drive resolution.

Requirements

  • Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science (or equivalent).
  • Experience with industry-standard simulation tools (e.g., Synopsys VCS, Cadence Xcelium, Mentor Questa).

Nice to have

  • Master's or Ph.D. in Electrical Engineering or Computer Science.
  • Academic or professional class projects or coursework in networking, communication protocols (e.g., Ethernet, PCIe, USB, AMBA/AXI, SPI, I2C, UART), or related areas.
  • Experience verifying high-speed serial interfaces or protocol-level IP blocks.
  • Familiarity with formal verification tools and techniques (e.g., JasperGold, VC Formal).
  • Experience with emulation and FPGA prototyping platforms (e.g., Palladium, Protium, Veloce).
  • Knowledge of scripting languages (Python, Perl, TCL) for automation of verification workflows and regression infrastructure.
  • Experience with power-aware verification (UPF/CPF) or mixed-signal verification.
  • Contributions to verification methodology development or published work in the field.

Skills

  • Automating generation of RTL from spec.
  • Evaluation of industry tools.
  • "The expected salary/wage range for this position is provided below.
  • Actual offer may vary from this range based upon geographic location, work experience, education/training, and/or skill level.

Compensation

  • USD 81,400 - 164,400 in California
  • The listed salary range reflects base salary.

Benefits

  • Health & Wellbeing
  • Creating verification plans with clear coverage goals and closure criteria.
  • Information about employee benefits offered in the US can be found at https://myhperewards.com/main/new-hire-enrollment.html

Company info

  • Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today's complex world. Our culture thrives on finding new and better ways to accelerate what's next. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good. If you are looking to stretch and grow your career our culture will embrace you. Open up opportunities with HPE.
  • Job Description:
  • We are seeking a Design / Verification Engineer with exposure to AIML methodologies to join our team. In this role, you will be responsible for developing and executing comprehensive verification strategies for complex digital designs using AIML enhanced methodologies. You will architect, build, and maintain UVM-based testbench environments, drive coverage-driven verification closure, and collaborate closely with design and system engineering teams to ensure silicon quality from RTL to tapeout. This is a high-impact position for someone who thrives on solving intricate design/ verification challenges using AIML methodologies.
  • Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work.
  • We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today's complex world.
  • Our culture thrives on finding new and better ways to accelerate what's next.
  • If you are looking to stretch and grow your career our culture will embrace you.
  • Open up opportunities with HPE.
  • We are seeking a Design / Verification Engineer with exposure to AIML methodologies to join our team.
  • In this role, you will be responsible for developing and executing comprehensive verification strategies for complex digital designs using AIML enhanced methodologies.
  • You will architect, build, and maintain UVM-based testbench environments, drive coverage-driven verification closure, and collaborate closely with design and system engineering teams to ensure silicon quality from RTL to tapeout.

Equal opportunity

  • Hewlett Packard Enterprise is EEO Protected Veteran/ Individual with Disabilities.
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This listing is sourced directly from Hpe's careers page and normalized into a canonical job model.