Celerocommunicationsinc
Principal Design Validation & Test (DVT) Engineer
Irvine, CA · Principal
Sponsorship not specifiedDetected 1 day ago
PythonData AnalysisEmbedded SystemsElectrical EngineeringSignal ProcessingLoad TestingFDA RegulatoryLeadershipCommunicationMentoring
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About the role
- As a key member of our engineering team, you will play a critical role in enabling first silicon, driving silicon characterization, and ensuring product readiness for customer deployment and high-volume production.
Responsibilities
- Lead post-silicon validation and characterization of complex ASICs and SoCs from first silicon through production release.
- Develop comprehensive validation plans covering functionality, performance, interoperability, compliance, stress testing, corner cases, and reliability.
- Validate high-speed interfaces including PCIe, Ethernet, SerDes, CXL, SPI, I²C, MDIO, and other industry-standard protocols.
- Debug complex hardware, firmware, RTL, and system-level issues while working closely with cross-functional engineering teams to identify root cause and drive timely resolution.
- Develop scalable Python-based automation frameworks for test execution, regression, silicon characterization, data analysis, and reporting.
- Validate firmware, bootloaders, device drivers, and hardware/software interfaces across multiple platforms.
- Lead debug reviews and provide technical direction for validation methodology, infrastructure, and best practices.
- Support early customer engagements by reproducing and resolving system-level issues and collaborating with applications engineering.
- Document validation results, silicon characterization data, debug findings, and production readiness reports.
Requirements
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline.
- 8+ years of hands-on post-silicon validation, DVT, or silicon bring-up experience with complex ASICs or SoCs.
- Strong understanding of silicon debug methodologies and structured root-cause analysis.
Nice to have
- Experience validating coherent optical DSPs, networking ASICs, Ethernet switch silicon, AI accelerators, GPUs, storage controllers, or high-speed communications devices.
- Strong knowledge of Ethernet, PCIe, OIF, IEEE, or related compliance specifications.
- Experience with PIPE, PCS, PMA, MAC, PHY, or other physical and protocol layers of high-speed interfaces.
- Familiarity with customer platform validation and hyperscale qualification processes.
- Experience mentoring engineers and leading technical initiatives across multiple engineering disciplines.
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