Samsung Semiconductor
Senior RTL Engineer, IO Die and Interconnect IP
San Jose, California, United States · Senior
Sponsorship not specified$138k-$206kDetected 3 days ago
PythonMachine LearningAgentic AIExcelRecruitingVerilogAvidResearchCommunicationProblem Solving
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odds of building a lasting career here
64Sponsors, lottery-bound
Cap-exempt (no lottery)0
Sponsors this role100
Entry-level history0
PERM / green-card track0
Lottery odds (Level IV)94
Fits your clock70
Sponsors, but it's cap-subject — you still face the weighted lottery (~61% per draw at Level IV). Good if you win; have a cap-exempt backup on your list.
Lottery odds assume a STEM candidate.
Personalize to your clock →Employer immigration record
from this employer's Department of Labor filings
Green-card filing pattern in this occupation
Context, not a finding about this posting: of this employer's 35 green-card filings in this occupation, 100% were for a worker who already held the job.
Green-card intent detected
Samsung Semiconductor, Inc. obtained a prevailing wage determination for Electrical Engineers in San Jose, CALIFORNIA on 2026-06-09. No matching green-card filing appears in our data yet. The determination expires in 1 day (2026-09-06), and a green-card filing must follow before then or the employer starts over.+1 more active determination on file
Green-card follow-through: 44%
Of 16 labor certifications old enough to have been used, 9 expired without the employer filing the next step. Median time from filing to decision: 496 days.100% of their filings were for a worker who already held the job.Only certifications past the 180-day window are counted — recent ones cannot have expired yet.
Files H-1B transfers
126 transfer filings in the last year, covering 435 workers. Median labor-condition decision: 7 days. An employer that already files transfers is one that can take over an existing H-1B.
Sourced from Department of Labor LCA, PERM and prevailing-wage disclosure data. Employer matching is by name, so figures may be split across an employer's legal entities. Absence of a filing means none appears in our copy of the data, not that none exists.
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About the role
- Please Note: To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period.
- Advancing the World's Technology Together Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more.
- We believe innovation and growth are driven by an inclusive culture and a diverse workforce.
Responsibilities
- Develop RTL (Verilog/SystemVerilog) for the IO die, integrating UCIe, PCIe, and other high-speed interconnect IP into a cohesive chiplet-based architecture.
- Define and implement die-to-die and chiplet interfaces using UCIe, ensuring protocol compliance and interoperability across chiplets.
- Own the microarchitecture and RTL for IO subsystems such as PCIe/CXL controllers, UCIe adapters, and interconnect fabric bridges.
- Collaborate with verification engineers to develop test plans and debug functional issues at the IP, subsystem, and die level.
- Work with architecture, PHY/SerDes, physical design, and software teams to close requirements across performance, power, area, and interoperability.
- Make design decisions out of a large design trade-off space across performance, power, latency, bandwidth, and cost.
- Develop and automate IP integration and RTL assembly flows using scripting and agentic AI tools and frameworks to improve turnaround time and quality of results.
- Communicate effectively with stakeholders, including users, partners, and management, to ensure that the die is delivered on time and within budget.
- An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
- You're collaborative, building relationships, humbly offering support and openly welcoming approaches.
Requirements
- Bachelor's with 5+ years, or Master's with 3+ years, or PhD's with 0+ years of industry experience.
- 5+ years of experience in RTL development (Verilog/SystemVerilog) for high-speed interconnect and IO subsystems.
- Experience modifying or customizing third-party interconnect IP (e.g., PCIe controller, PIPE, or PHY interface) to meet die-level requirements.
- Familiarity with UCIe and chiplet-based, multi-die architectures and die-to-die interconnect.
- Experience with SoC integration methodologies, IP packaging (e.g., IP-XACT), and on-chip interface protocols such as AXI, ACE, CHI, or APB.
- Experience in AI/ML workloads.
- Strong background in microarchitecture and RTL design for complex SoC and die integration.
- Hands-on experience integrating and configuring interconnect IP such as PCIe, CXL, UCIe, and die-to-die interfaces.
- Solid understanding of PCIe/CXL protocol stacks (transaction, data link, and physical layers) and the PIPE interface.
- Strong analytical and problem-solving skills
- Excellent communication and interpersonal skills
- Ability to work independently and as part of a team
Nice to have
- Proficiency in scripting (Tcl, Python, or Perl) for design integration and automation
- familiarity with agentic AI tools and frameworks is a plus.
Skills
- Advancing the World's Technology Together
- Join us in our passion to shape the future of computing!
- Daily onsite presence at our San Jose, CA office / U.S. headquarters in alignment with our Flexible Work policy.
Compensation
- $138,000 - $206,000 USD
Benefits
- This is in addition to our diverse package of benefits centered around the wellbeing of our employees and their loved ones.
- In addition to the usual Medical/Dental/Vision/401k, our inclusive rewards plan empowers our people to care for their whole selves.
- Enjoy Time Away You'll start with 4+ weeks of paid time off a year, plus holidays and sick leave, to rest and recharge.
- Care for Family Whatever family means to you, we want to support you along the way-including a stipend for fertility care or adoption, medical travel support, and virtual vet care for your fur babies.
- Prioritize Emotional Wellness With on-demand apps and free confidential therapy sessions, you'll have support no matter where you are.
- Embrace Flexibility Benefits are best when you have the space to use them.
- That's why we facilitate a flexible environment so you can find the right balance for you.
- Our onsite Café and gym, plus virtual classes, make it easier.
Company info
- Our Commitment to Innovation and Fairness At Samsung Semiconductor, we use Artificial Intelligence (AI) tools in the recruitment process to enhance efficiency.
Equal opportunity
- Employment Policy
- Samsung Semiconductor takes pride in being an equal opportunity workplace dedicated to fostering an environment where all individuals feel valued and empowered to excel, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status.
- When selecting team members, we prioritize talent and qualities such as humility, kindness, and dedication.
- We extend comprehensive accommodations throughout our recruiting processes for candidates with disabilities, long-term conditions, neurodivergent individuals, or those requiring pregnancy-related support.
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This listing is sourced directly from Samsung Semiconductor's careers page and normalized into a canonical job model.