Neuralink
Digital Verification Engineer
South San Francisco, California, United States · Contract
Stay score
odds of building a lasting career here
Sponsors, but it's cap-subject — you still face the weighted lottery (~61% per draw at Level IV). Good if you win; have a cap-exempt backup on your list.
Lottery odds assume a STEM candidate.
Personalize to your clock →H-1B wage level
the lottery is wage-weighted — each level is one more entry
$7,528 more — $138,528 — moves this role to Level II and 2 lottery entries. That figure is inside the range the employer already advertised.
Based on the DOL prevailing wage for this occupation and worksite, a base salary of $138,528 would place this position at wage Level II. That figure is within the posted range, and I'd like to target it. This role classifies under "Electronics Engineers, Except Computer" for prevailing-wage purposes.
DOL prevailing wage, 2026-27 wage year · Electronics Engineers, Except Computer (17-2072) · San Francisco-Oakland-Fremont, CA. Wage level is derived by USCIS from the offered wage, occupation and worksite; the occupation shown is inferred from the job title.
Employer immigration record
from this employer's Department of Labor filings
Files H-1B transfers
Sourced from Department of Labor LCA, PERM and prevailing-wage disclosure data. Employer matching is by name, so figures may be split across an employer's legal entities. Absence of a filing means none appears in our copy of the data, not that none exists.
Community outcomes
No reports yet — be the first to help the next applicant.
About the role
- This position offers a rare and unique opportunity to have a high impact in realizing state-of-the-art brain-computer interfaces.
- We have crafted a team of exceptional engineers whose mission is to push the frontiers of what is possible today and define the future.
Responsibilities
- The team delivers architecture and logic implementation of digital modules with a strong focus in high-throughput low-power digital signal processing (DSP).
Requirements
- Minimum 3 years of experience in digital ASIC verification.
- Bachelor's degree in a technical field OR equivalent experience.
Nice to have
- Experience in formal verification.
- Functional modeling experience and logic verification with SystemVerilog, SystemC/C++.
- Experience with IEEE-1801 (UPF) based design simulation flows
- Experience with low power gate level simulations
- Exposure with low power formal verification flows
- Strong hands-on experience in verification methodologies such as UVM
- Knowledge of ARM/RISC-V processor, AMBA bus
- Knowledge of power aware verification
Compensation
- The anticipated base salary for this position is expected to be within the following range.
- Your actual base pay will be determined by your job-related skills, experience, and relevant education or training.
- As such, in addition to base salary, Neuralink offers equity compensation (in the form of Restricted Stock Units (RSU)) for all full-time employees.
- $131,000 - $243,000 USD
Benefits
- Full-time employees are eligible for the following benefits listed below.
- Excellent medical, dental, and vision insurance through a PPO plan
- Commuter benefits
- Equity (RSUs) *Temporary Employees & Interns excluded
- Parental leave *Temporary Employees & Interns excluded
- Flexible time off *Temporary Employees & Interns excluded
Company info
- We are creating devices that enable a bi-directional interface with the brain.
- These devices allow us to restore movement to the paralyzed, restore sight to the blind, and revolutionize how humans interact with their digital world.
- We are looking for ASIC Design Verification Engineers with strong CPU, ASIC design and verification fundamentals to work in Neuralink's System-on-Chip (SoC) department under the Implant Team.
This listing is sourced directly from Neuralink's careers page and normalized into a canonical job model.