Solidigm

Design Automation / Standard Cell Characterization Engineer

San Jose, CA, United States

Sponsorship not specified$121k-$194kDetected 4 days ago

PythonBashCadenceVerilogElectrical Engineering

About the role

Headquartered in Rancho Cordova, California, Solidigm combines elements of an established, successful technology company with the spirit, agility, and entrepreneurial mindset of a start-up.
In addition to the U.S. headquarters and other facilities in the U.S., the company has international presence in Asia, Europe, and the Americas.
We want a diverse team of dedicated professionals who will not just be Solidigm team members but contribute to how we shape the future of the organization.

Deliver complete library collaterals (.lib, LEF, GDS, CDL, Verilog, NDM, etc.)
Develop and enhance DA automation frameworks
Build scalable automation using Python, Perl, Tcl, and shell scripting
Drive library QA and validation infrastructure
Develop QA flows for cross-collateral consistency (lib, netlists, layouts, timing views)
Implement equivalency checks, validation dashboards, and automated reporting
Support Digital Frontend (DFE) enablement
Partner with frontend teams to ensure high-quality library deliverables for synthesis and STA
Enable flows for Design Compiler / Fusion Compiler and PrimeTime integration
Validate timing models, constraints, and library views for RTL-to-Gates and timing closure flows

5+ years of experience in standard cell library characterization and validation, including generation and delivery of production-quality collaterals
5+ years of experience in design automation and EDA flow development, with a focus on scalable and maintainable methodologies
Hands-on experience with digital frontend flows, including synthesis and static timing analysis (STA)

This listing is sourced directly from Solidigm's careers page and normalized into a canonical job model.