Astera Labs Inc.

Astera Labs Inc.

Principal FW/SW Engineer

Toronto, Ontario, Canada · Principal · Full-time

Sponsorship not specifiedDetected 4 days ago
AlgorithmsThermal AnalysisEmbedded SystemsLeadershipCollaboration

Stay score

odds of building a lasting career here

42Risky
Cap-exempt (no lottery)0
Sponsors this role100
Entry-level history0
PERM / green-card track0
Lottery odds40
Fits your clock70

Thin sponsorship signal and lottery-bound. A low-probability bet with your clock running. Prioritize cap-exempt roles and proven entry-level sponsors first.

Lottery odds assume a STEM candidate.

Personalize to your clock →

Employer immigration record

from this employer's Department of Labor filings

Files H-1B transfers

28 transfer filings in the last year, covering 28 workers. Median labor-condition decision: 7 days. An employer that already files transfers is one that can take over an existing H-1B.

Sourced from Department of Labor LCA, PERM and prevailing-wage disclosure data. Employer matching is by name, so figures may be split across an employer's legal entities. Absence of a filing means none appears in our copy of the data, not that none exists.

Community outcomes

No reports yet — be the first to help the next applicant.

About the role

  • Join Astera Labs' Signal Connectivity Engineering team as a Principal Engineer shaping the firmware and software that makes advanced connectivity products adaptive, reliable, and production-ready.
  • This is a high-impact role at the intersection of embedded systems, mixed-signal hardware, and Ethernet physical-layer behavior.
  • You will work across architecture, lab debug, automation, and customer integration while partnering with silicon, analog, systems, validation, and applications teams.

Responsibilities

  • Own the embedded firmware stack from hardware abstraction and device drivers through management interfaces, diagnostics, and customer-facing APIs.
  • Design firmware for adaptive equalization, gain control, calibration, link training, PLL/CDR feedback, thermal management, and device telemetry.
  • Architect control algorithms, state machines, and tuning flows that manage analog and high-speed interfaces across process, voltage, and temperature variation.
  • Investigate register accesses, embedded SDK behavior, link state machines, PHY telemetry, logs, and real-hardware measurements to identify root causes and deliver targeted fixes.
  • Partner with system validation to develop test plans, automate characterization flows, and verify firmware across corner cases and product configurations.
  • Support customer bring-up, field issue triage, and deployment readiness in collaboration with applications, platform, and silicon teams.
  • Set technical direction, lead architecture and tradeoff discussions, and balance performance, code size, maintainability, and time to market.

Compensation

  • Occasional travel to Astera Labs' San Jose headquarters, approximately twice per year, for chip bring-up and project coordination

This listing is sourced directly from Astera Labs Inc.'s careers page and normalized into a canonical job model.