Altera
Clocking Architect
San Jose, California, United States · Senior
Sponsorship not specified$187k-$271kDetected 30 days ago
PythonNode.jsMachine LearningCadenceFPGAElectrical EngineeringLeadership
About the role
- The ideal candidate brings deep hands-on expertise in PCIe, High-Speed Memory I/O, ARM, Ethernet, and SerDes clocking domains, combined with mastery of SDC constraint authoring for both functional and DFT modes.
- This is a high-visibility, high-impact role with direct influence over silicon architecture decisions.
Responsibilities
- Own and drive the complete clocking architecture for Altera's FPGA/SoC devices, including clock tree topology, domain partitioning, frequency planning, and PLL/DLL resource allocation.
- Deliver the clocking specification, clock architecture diagrams, and constraint management documentation as program-level deliverables.
- Collaborate with RTL, physical design, timing, and verification teams to ensure the clock architecture is correctly modeled and implemented across all design stages.
- support SRIS/SRNS topologies and PCIe reset/power management clocking sequences.
- ARM Subsystems (Cortex-A/M/R, DSU, CMN Interconnect): Own core, peripheral, and AMBA bus clock hierarchies
Requirements
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical field.
- Proven ownership of full-chip and subsystem-level clocking architecture on high-complexity SoC or FPGA devices.
- Deep expertise across PCIe (Gen4/5/6), DDR5/LPDDR5/HBM, ARM CoreLink/CMN, Ethernet (1G-400G), Configuration interfaces, and SerDes clocking.
- Demonstrated experience architecting clocking for ML/AI accelerator silicon: multi-frequency compute/memory/interconnect clock planes, DVFS, and HBM/LPDDR5X integration.
- Proficiency with CDC verification tools (SpyGlass CDC, JasperGold CDC, Questa CDC) including waiver management and RTL coding guideline enforcement.
- Experience with low-power design methodologies (UPF/CPF) and their interaction with clock gating and multi-voltage power domains.
- We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.
- Applicants must be eligible for any required U.S. export authorizations.
- 12+ years of industry experience in physical design, SoC/FPGA design, or clocking architecture, with silicon tape-outs at 7nm or below.
Nice to have
- FPGA or programmable logic background with understanding of fabric clocking resources (PLLs, global/regional clock networks, GCLK/RCLK routing).
- Experience with clocking for hard IP subsystems within FPGA SoC devices (e.g., HPS, PCIe hard blocks, memory controllers).
- Experience with formal CDC verification and model checking (VC Formal) for synchronizer correctness proofs.
- Familiarity with PLL/DLL characterization, frequency margining, jitter budget analysis, and SSC validation.
- Knowledge of IEEE 1500, P1687 (IJTAG), and their clocking implications for embedded DFT instrumentation.
- Experience with multi-die/chiplet clocking architectures (UCIe, BoW, AIB) and die-to-die CDC management.
- Scripting proficiency in Tcl and/or Python for constraint automation, CDC report parsing, and custom analysis flows.
- Familiarity with Intel/Altera FPGA architecture (Stratix, Agilex product families) a significant advantage.
Skills
- About Altera
Compensation
- The pay range below is for Bay Area California only.
- Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc.
- We also offer incentive opportunities that reward employees based on individual and company performance.
- $187,000 - $270,700 USD
Benefits
- medical, dental, vision, 401(k) with company match, and paid parental leave.
- Flexible hybrid work model and dedicated professional development investment.
This listing is sourced directly from Altera's careers page and normalized into a canonical job model.