Astera Labs Inc.

Astera Labs Inc.

Principal Package Signal & Power Integrity

San Jose, California, United States · Principal

Sponsorship not specifiedDetected 1 day ago
ANSYSPCB DesignCadenceElectrical EngineeringMentoring

Stay score

odds of building a lasting career here

42Risky
Cap-exempt (no lottery)0
Sponsors this role100
Entry-level history0
PERM / green-card track0
Lottery odds40
Fits your clock70

Thin sponsorship signal and lottery-bound. A low-probability bet with your clock running. Prioritize cap-exempt roles and proven entry-level sponsors first.

Lottery odds assume a STEM candidate.

Personalize to your clock →

Employer immigration record

from this employer's Department of Labor filings

Green-card filing pattern in this occupation

Context, not a finding about this posting: of this employer's 5 green-card filings in this occupation, 100% were for a worker who already held the job.

Files H-1B transfers

28 transfer filings in the last year, covering 28 workers. Median labor-condition decision: 7 days. An employer that already files transfers is one that can take over an existing H-1B.

Sourced from Department of Labor LCA, PERM and prevailing-wage disclosure data. Employer matching is by name, so figures may be split across an employer's legal entities. Absence of a filing means none appears in our copy of the data, not that none exists.

Community outcomes

No reports yet — be the first to help the next applicant.

About the role

  • As a Principal Package Signal & Power Integrity Engineer at Astera Labs, you will serve as a senior technical leader responsible for architecting, optimizing, and signing off package SIPI solutions for next-generation connectivity products.

Responsibilities

  • Define package SIPI architecture and design strategy for high-performance connectivity products, including PCIe 5.0/6.0/7.0, CXL, Ethernet, 200G/400G+ SerDes, and die-to-die interconnect.
  • Perform package and system-level SI and PI simulations using industry-standard simulation software such as HFSS, SIwave, and Keysight ADS to develop, optimize, and sign off package electrical models, validate package architecture and designs, and ensure robust signal and power integrity across chip-package-board systems.
  • Lead cross-functional execution across silicon team, package design, marketing and APPs, PCB board team, validation team, package manufacturing, and external substrate/OSAT partners, managing technical tradeoffs among SIPI performance, cost, DFM, yield, etc., and deliver packaging solutions on schedule.
  • Drive simulation-to-measurement correlation strategy, ensuring strong alignment between EM extraction, system-level models, and lab validation (VNA, TDR, high-speed oscilloscope), continuously improving model accuracy, simulation efficiency, and SIPI signoff criteria.
  • Own SIPI simulation and signoff for advanced packaging platforms, including chiplet-based packages, 2.5D/3D integration, silicon interposers, and bridge-based interconnect, by leading simulations for D2D interconnect (e.g., UCIe), multi-die PDN, micro-bump modeling, TSV/interposer modeling, and multi-die CPM co-simulation.
  • Establish SIPI modeling standards, design rules, review checklists, automation flows, and signoff methodologies to improve execution efficiency, while mentoring engineers across the organization.

Requirements

  • 10+ years of experience in signal integrity, power integrity, package electrical design, or chip-package-board co-design for high-performance semiconductor products.
  • Deep expertise in package SIPI modeling, analysis, optimization, and signoff across the chip-package-board system, for high-speed SerDes, PCIe, CXL, Ethernet, etc.
  • Strong experience with PCIe 5.0/6.0, PAM4 SerDes channel design, high-speed S-parameter extraction, package model development, eye-diagram analysis, return/insertion-loss optimization, and crosstalk analysis.
  • Hands-on expertise with EM extraction and SIPI simulation tools such as ANSYS HFSS, SIwave, Q3D, 3D Layout, Keysight ADS, Cadence Sigrity, or equivalent tools.
  • Demonstrated ability to correlate simulation to lab measurement (VNA, TDR, high-speed oscilloscope).
  • Strong understanding of tradeoffs between SIPI performance, cost, reliability, and manufacturability.
  • Experience leading vendor engagements and managing technical execution through production ramps.

Nice to have

  • Experience influencing silicon floor planning, bump map definition, SerDes and power-grid planning, package escape strategy, and PCB breakout from a SIPI perspective.
  • Experience with automation and scripting for SIPI modeling flow.
  • Exposure to Allegro Package Designer (APD) for hands-on substrate editing.
  • Knowledge on traditional FCBGA type package and advanced package (chiplet/2.5D/3D) manufacturing and assembly process flows

Skills

  • Labs (NASDAQ:
  • ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions.
  • Discover more at www.asteralabs.com.

Compensation

  • The base salary range is $203,000 USD – $230,000 USD.
Apply directly at Astera Labs Inc. →Create a free account for alerts like thisView Astera Labs Inc. immigration profile

This listing is sourced directly from Astera Labs Inc.'s careers page and normalized into a canonical job model.