Altera
Transceivers & Protocol IP Application Engineer
San Jose, California, United States
Stay score
odds of building a lasting career here
Sponsors, but it's cap-subject — you still face the weighted lottery (~61% per draw at Level IV). Good if you win; have a cap-exempt backup on your list.
Lottery odds assume a STEM candidate.
Personalize to your clock →H-1B wage level
the lottery is wage-weighted — each level is one more entry
The bottom of this range ($149,100) is below the Level I prevailing wage of $152,797. An H-1B cannot be filed below the prevailing wage, so an offer at the floor of this band could not be sponsored as posted.
Based on the DOL prevailing wage for this occupation and worksite, a base salary of $187,075 would place this position at wage Level II. That figure is within the posted range, and I'd like to target it. This role classifies under "Software Developers" for prevailing-wage purposes.
DOL prevailing wage, 2026-27 wage year · Software Developers (15-1252) · San Jose-Sunnyvale-Santa Clara, CA. Wage level is derived by USCIS from the offered wage, occupation and worksite; the occupation shown is inferred from the job title.
Employer immigration record
from this employer's Department of Labor filings
Green-card intent detected
Files H-1B transfers
Sourced from Department of Labor LCA, PERM and prevailing-wage disclosure data. Employer matching is by name, so figures may be split across an employer's legal entities. Absence of a filing means none appears in our copy of the data, not that none exists.
Community outcomes
No reports yet — be the first to help the next applicant.
About the role
- Provide expert technical guidance on Altera high-speed transceiver PHYs and protocol IP, including architecture, IP configuration, clocking, reset, PLL/CDR behavior, channel placement, link bring-up, and system integration.
- Review customer system architectures, schematics, constraints, RTL, IP parameterization, simulation results, timing reports, and hardware measurements; identify risks and recommend practical corrective actions.
- Diagnose problems spanning FPGA IP, transceiver configuration, firmware, reference clocks, signal integrity, resets, data paths, protocol behavior, Quartus flows, and customer application logic.
Responsibilities
- Support customer designs using protocols such as Ethernet, PCIe, JESD204B/JESD204C, CPRI/eCPRI, Interlaken, DisplayPort, HDMI, SerialLite, and PMA/FEC Direct PHY configurations, as applicable to the assigned product portfolio.
- Reproduce and isolate customer issues using Quartus Prime, design examples, System Console, Signal Tap, Transceiver Toolkit, simulation environments, development kits, and laboratory equipment.
- Own technical cases from initial analysis through resolution, maintaining clear problem statements, evidence, investigation plans, customer updates, and closure documentation.
- Collaborate with engineering teams to escalate suspected product, IP, silicon, software, or documentation defects with sufficient reproduction data and technical analysis.
- Drive issue resolution and corrective actions, including improvements to design examples, user guides, application notes, knowledge-base content, tools, and customer workflows.
- Develop scripts, test collateral, reference designs, and automation in Python, Tcl, Bash, or similar languages to improve debug efficiency and customer adoption.
Requirements
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical discipline.
- Hands-on experience with FPGA design flows and hardware debugging using Quartus Prime or a comparable FPGA development environment.
- Working knowledge of high-speed serial interfaces, transceiver PHY concepts, clocking, PLLs, CDRs, resets, equalization, link training, channel bonding, and signal-integrity fundamentals.
- Experience reading and debugging RTL, IP configuration files, timing constraints, simulation waveforms, register maps, and hardware logs.
- Proficiency in at least one hardware description language, such as Verilog, SystemVerilog, or VHDL.
- Scripting or software-development experience in Python, Tcl, Bash, C, or C++.
- We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.
- Applicants must be eligible for any required U.S. export authorizations.
- Professional experience in FPGA applications, high-speed digital design, ASIC/FPGA validation, protocol IP development, field application engineering, or technical customer support.
- Strong analytical, problem-solving, prioritization, and technical writing skills.
- Ability to communicate clearly with customers and cross-functional engineering teams, including when the root cause is still under investigation.
- Ability to manage multiple technical issues and priorities while maintaining ownership, responsiveness, and high-quality records.
Nice to have
- Experience with Altera Agilex, Stratix, Arria, or Cyclone FPGA families and associated transceiver tiles or PHY architectures.
- Knowledge of Ethernet MAC/PCS/FEC, PCIe, JESD204, CPRI/eCPRI, Interlaken, DisplayPort, HDMI, or other high-speed protocol IP.
- Experience with Quartus Prime Pro, Platform Designer, System Console, Signal Tap, Transceiver Toolkit, ModelSim, Questa, or similar EDA and debug tools.
- Experience performing board-level bring-up, eye-diagram or BER analysis, loopback testing, protocol analysis, or lab-based transceiver characterization.
- Experience working with regional application engineering, field application engineering, silicon, IP, software, validation, and technical communications organizations.
- Shift 1 (United States of America)
- San Jose, California, United States
- Posting Statement:
Skills
- Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc.
Compensation
- The pay range below is for Bay Area California only.
- Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc.
- We also offer incentive opportunities that reward employees based on individual and company performance.
Company info
- Altera is seeking a technically strong Transceivers & Protocol IP Application Engineer to be based in San Jose California Altera Office to help customers and partners successfully adopt Altera FPGA transceiver and protocol IP solutions.
- We also offer incentive opportunities that reward employees based on individual and company performance.
- Provide technical training, workshops, design reviews, demonstrations, and hands-on enablement for customers, partners, sales teams, field application engineers, and internal engineering teams.
This listing is sourced directly from Altera's careers page and normalized into a canonical job model.