Nuvacore

Nuvacore

CPU Physical Design (RTL Feasibility)

Austin, TX · Senior

Sponsorship not specified$140k-$250kDetected 35 days ago
PythonAgentic AICadenceCommunication

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odds of building a lasting career here

59Sponsors, lottery-bound
Cap-exempt (no lottery)0
Sponsors this role80
Entry-level history0
PERM / green-card track0
Lottery odds (Level IV)94
Fits your clock70

Sponsors, but it's cap-subject — you still face the weighted lottery (~61% per draw at Level IV). Good if you win; have a cap-exempt backup on your list.

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Files H-1B transfers

8 transfer filings in the last year, covering 8 workers. Median labor-condition decision: 7 days. An employer that already files transfers is one that can take over an existing H-1B.

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About the role

  • As a CPU Physical Design (PD) Engineer, you will participate in the following:

Responsibilities

  • Nuvacore is building ground-up high performance, low-power CPU for next-generation compute workloads.
  • As physical design engineers focused on design feasibility you will focus on providing power, performance, and area feedback to the RTL team to ensure the design achieves all metrics and targets.
  • Lead RTL/micro-architecture feasibility studies, providing actionable feedback to design teams.
  • Drive PPA outcomes for CPU units with a focus on timing closure and power optimization.
  • Collaborate cross-functionally with CPU unit owners, custom circuit designers, CAD, RTL/micro-architecture, and performance modeling teams.
  • Own the RTL intake process for the PD team, enforcing quality standards and ensuring design readiness before RTL handoff.

Requirements

  • Hold a BS or MS degree with 12+ years of experience (for Lead roles) or 5+ years of experience (for Individual Contributor roles) in CPU physical design.
  • Experience in CPU RTL feasibility, including RTL synthesis and floor planning.
  • Deep expertise in timing analysis and timing ECO.
  • Proficiency with Synopsys or Cadence EDA tools for PD in CPU design context.
  • Track record of driving PPA optimization for CPU units through effective RTL feedback and cross-functional collaboration.
  • Experience with some CPU units as block ownership taking from RTL to GDS (Tape-out).
  • Proficiency in Python, Perl, and TCL for design automation and flow development.
  • Experience in using Agentic AI tools for productivity and automation.

Compensation

  • $140k-$250k

This listing is sourced directly from Nuvacore's careers page and normalized into a canonical job model.