Eridu AI

Physical Design Engineer

Saratoga, CA

Sponsorship not specifiedDetected 23 days ago

PythonLinuxVerilogCommunicationProblem Solving

About the role

Today's AI performance is frequently limited by communication bottlenecks.
We do this while simultaneously reducing capital and power costs, improving reliability, simplifying operations and speeding AI data center deployments for faster time to revenue.
The company's solutions and value proposition have been widely validated by leading hyperscalers.

Define the Physical Assembly of SOC. involving all aspects of physical design functions such as P&R, timing, floorplan, clocking, electrical analysis, and power.
Design and Architect Top Level and block Level Floor planning of the entire SoC.
Work extensively with Micro-architects to perform feasibility studies and explore performance, power & area (PPA) tradeoffs for design closure.
Develop physical design methodologies and customize recipes across various implementation steps to optimize PPA.
Work with a multi-functional engineering team to implement and validate physical design by running all signoff flows such as Timing, Power, EM/IR, PDV.
Familiarity with logic & physical design principles to drive low-power & higher-performance designs.
About Eridu Eridu is a Silicon Valley-based hardware startup pioneering infrastructure solutions that accelerate AI data centers to deliver Faster AI.
Eridu delivers multiple industry-first innovations across silicon, packaging, software, and systems to deliver a step function in AI networking - a network switch that is an order of magnitude improvement in bandwidth and radix versus today's "state of the art" switches.

Proficiency in Synthesis design constraints (SDC).
Sound Proficiency in either Innovus or Synopsys Fusion Compiler required.
Proficiency in synthesis, Floor planning Power Planning and Timing closure are required.
Master's Degree or bachelor's degree in EE with a minimum of 10+ years of experience.
Prior experience of multiple tape-out in deep submicron 7nm or below is required.

Prior experience with large skew optimized clock tree designs like H-Tree preferred.
Clock Grid exposure is a plus.

Unix, Perl, Python, and TCL.
Good understanding of device physics and experience in deep sub-micron technologies 7nm or below.
Knowledge of Verilog and System Verilog.
Excellent skills in problem solving, written and verbal communication, excellent organization skills, and highly self-motivated.
Ability to work well in a team and be productive under aggressive schedules.
Prior experience of multiple tape-out in deep submicron 7nm or below is required.

INFN), Lightera (acq. by Ciena), Gainspeed (acq. by Nokia) and Mojo Vision (the world's leading micro-LED company).
Eridu has also assembled a world class IP, design and manufacturing ecosystem to execute on its vision, and counts TSMC as a key partner in our journey.

This listing is sourced directly from Eridu AI's careers page and normalized into a canonical job model.