Western Digital
HDD Servo Processing Subsystem Architecture Lead
San Jose, CA, United States
Sponsorship not specifiedDetected 23 days ago
C++MATLABAlgorithmsCloud PlatformsCI/CDBudgetingFPGAEmbedded SystemsElectrical EngineeringSignal ProcessingControlsSimulinkVoIPLeadershipCommunicationProblem SolvingActuators
About the role
- It's real systems, at real scale, people solving some of the hardest challenges in technology today.
- Join us and let's shape the future of data.
- This position offers the opportunity to shape the future of storage technology while leading cross-functional teams across multiple locations and technical disciplines.
Responsibilities
- Define and maintain a future-state servo real-time compute architecture and ISA that scales from single to multiple concurrent data streams and supports concurrent control of multiple actuators and heads, with explicit guidance to SoC and servo teams on power, area, and performance trade-offs
- Co-lead SoC microarchitecture decisions affecting servo compute, including core count and placement, memory hierarchy, interconnect design, and dynamic control accelerators, ensuring that FPGA prototype work and accelerator designs map cleanly into production-ready firmware and tools models
- Own servo compute resource management and budgeting, including instruction/data memory allocation, processor cycle and path-length limits, and regression thresholds; drive adherence through continuous integration practices to prevent late-stage resource conflicts
- Lead the co-design of firmware platform architecture, including core control-loop implementations, multi-cluster and multi-actuator orchestration, and cross-generation stability, ensuring deterministic real-time performance across multiple SoC generations
- Drive evolution of the servo compute tooling ecosystem-including internal compiler, real-time compute platform simulator, Renode-based system simulation, debug and diagnostics tools, and profiling/debug flows-to support multi-cluster, multi-stream characterization and debugging by servo, manufacturing, and validation teams
- Coordinate across geographically distributed teams (servo firmware (FW), SoC architecture/design, recording subsystem/algorithms, servo tools, manufacturing FW, and test) to align platform decisions with program risk, schedules, yield, and customer experience objectives
- Deliver a major multi-stream and multi-actuator capability that meets control performance and power targets on a new SoC generation, demonstrating the viability of the defined architecture and ISA
- Analyze and optimize servo loop performance through modeling, simulation, and real-world validation using tools such as MATLAB and Simulink, with focus on multi-actuator control scenarios and high-bandwidth data paths
- Develop and document architectural standards, design guidelines, and best practices for servo subsystem development, including guidance on HAMR, laser, spacing, and read/write channel control parameter mapping to the compute platform
- Mentor and develop junior engineers, fostering a culture of technical excellence, platform thinking, and continuous improvement in servo compute architecture
Requirements
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or an equivalent degree and professional experience
- Master's degree or relevant professional certification (e.g., in embedded systems, real-time architecture) desirable
- 5+ years of experience as a project technical leader or in senior technical leadership roles, demonstrating strong leadership and commitment to delivering results
- Demonstrated experience with FPGA and/or ASIC design for servo processing applications
- Every interaction, every model, every system generates data that must be stored, managed, and made accessible over time.
Skills
- Advanced programming skills in C/C++ and experience with hardware description languages (HDL)
- Proficiency with MATLAB, Simulink, and other modeling and simulation tools
- Deep expertise with specialized simulation and development tools including Renode, Verilator, and LLVM
- Solid understanding of hardware-software co-design and system-level integration
- Excellent analytical and problem-solving skills with meticulous attention to detail
- Familiarity with industry standards and best practices in storage technology
- Ability to work effectively in a fast-paced, collaborative environment
- Our non-discrimination policy applies to all aspects of employment.
- Our pay transparency policy is available HERE
- WD thrives on the power and potential of diversity.
- Please contact us at jobs.accommodations@wdc.com to advise us of your accommodation request.
Compensation
- The salary range is what we believe to be the range of possible compensation for this role at the time of this posting.
- We may ultimately pay more or less than the posted range and this range is only applicable for jobs to be performed in California, Colorado, New York or remote jobs that can be performed in California, Colorado and New York.
- This range may be modified in the future.
- If your position is non-exempt, you are eligible for overtime pay pursuant to company policy and applicable laws. You may also be eligible for shift differential pay, depending on the shift to which you are assigned.
- You will be eligible to be considered for bonuses under either WD's Short Term Incentive Plan ("STI Plan") or the Sales Incentive Plan ("SIP") which provides incentive awards based on Company and individual performance, depending on your role and your performance.
- You may be eligible to participate in our annual Long-Term Incentive (LTI) program, which consists of restricted stock units (RSUs) or cash equivalents, pursuant to the terms of the LTI plan.
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