OLIX
AMS Engineer
Austin, TX
Sponsorship not specifiedDetected 33 days ago
PythonVerilogElectrical EngineeringSignal Processing
About the role
- We are designing silicon for a new and innovative breakthrough AI computing solution using optics and high-speed interconnect.
Responsibilities
- Own the verification strategy and test plan for our mixed-signal subsystems, from block level through subsystem and top-level integration.
- Develop and validate analog behavioral models against transistor-level references, owning the model-vs-schematic equivalence checks that keep the abstraction honest.
- Build self-checking testbenches and reusable verification components for analog/digital interactions: CDR lock, adaptation and calibration loop convergence, mode and power-state transitions, clock dividers, deserializers, and clock-domain crossings.
- Drive AMS co-simulation flows (Spice/FastSpice coupled with digital simulators) and own their setup, performance, and runtime trade-offs.
- Debug and root-cause failures across the analog/digital boundary, including discrepancies between behavioral and transistor-level results, and drive them to closure.
- Partner with analog and DSP designers to review specs, pin down interface contracts, and translate analog intent into checkable models, assertions, and tests.
- Build and maintain regression infrastructure and flow automation, and improve AMS simulation throughput.
Requirements
- Proficiency in SystemVerilog, with solid assertion-based verification skills and the ability to architect self-checking testbenches and reusable verification components.
- Comfort reading analog schematics and specifications and collaborating directly with analog and DSP designers.
- Define the modeling approach and fidelity tiers - decide what gets a real-number model, what needs Verilog-AMS, and where transistor-level co-sim is required - and document the accuracy/runtime trade-offs.
Nice to have
- Strong working knowledge of high-speed SerDes / wireline architectures - CDR and clock recovery, equalization (CTLE, DFE), PLLs and clocking, samplers/slicers, and serialization/deserialization.
- Experience verifying calibration and adaptation loops (offset and I/Q calibration, DFE tap adaptation) and clock-domain-crossing logic between recovered and core clock domains.
- UVM or other constrained-random, metric-driven verification experience for the digital control wrapped around analog blocks.
- Scripting for regression and flow automation (Python, TCL, Make).
- Track record of mixed-signal IP sign-off through tape-out, plus silicon bring-up and measurement correlation.
- A clear understanding of where AMS verification ends and transistor-level performance sign-off begins.
- You're not just joining the mission
- you're owning a piece of it
Compensation
- Commensurate with your experience, skills, and location
Benefits
- Employer-contributed retirement plans to help you build long-term financial security
- Meaningful stock options.
- To minimise your commute and maximise your life, we offer an annual Living-Local Bonus if your residence is within 20 minutes of the office
- Define functional coverage and assertions that target analog corner behavior - saturation, overflow, polarity, loop stability, settling - not just digital state.
- Own block- and subsystem-level verification sign-off for tape-out, including coverage closure and a clear statement of what AMS did and did not verify (functional vs. performance).
Visa & Work Authorization
- export control regulations, candidates' eligibility to work at OLIX depends on their most recent citizenship or permanent residency status
This listing is sourced directly from OLIX's careers page and normalized into a canonical job model.