Astera Labs Inc.

Astera Labs Inc.

Sr. Principal Program Manager, ASIC Post-Silicon Engineering

San Jose, California, United States · Principal

Sponsorship not specified$205k-$250kDetected 4 days ago
JiraConfluenceStakeholder ManagementSupply ChainFPGALeadershipCommunication

About the role

  • The ideal candidate brings deep experience leading technically complex semiconductor or systems programs involving silicon, firmware, software, platform, validation, manufacturing, and customer readiness.
  • They are highly effective at driving cross-functional alignment, managing program risk, and communicating crisply with both engineering teams and executive stakeholders.

Responsibilities

  • Own the integrated post-silicon program plan from silicon power-on through bring-up, validation, qualification, customer sampling, and RTM, ensuring alignment across silicon, firmware/software, platform, compliance, production test and manufacturing milestones.
  • Drive program schedules, budgets, resources, interdependencies, and risk management, balancing scope, schedule, and cost trade-offs while maintaining clear communication with executives and key stakeholders.
  • Manage phase-gate exit criteria, readiness checkpoints, dashboards, and decision forums to support predictable delivery and rapid cross-functional decision-making.
  • Lead cross-functional execution across engineering, product, operations, quality, manufacturing, and customer-facing teams.
  • Drive internal technical issue resolution through structured triage, escalation management, milestone reviews, and executive reporting
  • surface risks early, drive accountability, and enable timely decisions and recovery plans.
  • Own customer sampling readiness, including sample allocation, validation exit criteria, firmware/software readiness, known-issue documentation, errata, release notes, reference platforms, and validation summaries.
  • Drive customer-facing issue resolution and escalation management in partnership with product management, applications engineering, sales, quality, and engineering teams, ensuring materials and support plans are aligned with deployment.
  • Lead cross-functional execution from engineering validation through RTM phase-gate exit.
  • Drive internal technical issue resolution through structured triage, escalation management, milestone reviews, and executive reporting; surface risks early, drive accountability, and enable timely decisions and recovery plans.

Requirements

  • Strong experience leading post-silicon execution for complex ASIC, SoC, FPGA, SerDes, Ethernet, PCIe, CXL, networking, AI infrastructure, cloud, data center, or high-performance compute products.
  • Experience managing FW development cycle, experience with JIRA, Confluence, dashboards, issue-tracking systems.
  • Proven experience managing executive communications, program dashboards, milestones, dependencies, technical risks, issue escalations, and launch-readiness reviews.
  • Ability to operate effectively in fast-paced, ambiguous, technically complex environments with aggressive product schedules.

Compensation

  • Salary range is $205,000 to $250,000 depending on experience, level, and business need.
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