Astera Labs Inc.
Principal Physical Design Engineer, Methodology
San Jose, California, United States · Principal
Stay score
odds of building a lasting career here
Sponsors, but it's cap-subject — you still face the weighted lottery (~61% per draw at Level IV). Good if you win; have a cap-exempt backup on your list.
Lottery odds assume a STEM candidate.
Personalize to your clock →H-1B wage level
the lottery is wage-weighted — each level is one more entry
$2,408 more — $187,408 — moves this role to Level III and 3 lottery entries. That figure is inside the range the employer already advertised.
Based on the DOL prevailing wage for this occupation and worksite, a base salary of $187,408 would place this position at wage Level III. That figure is within the posted range, and I'd like to target it. This role classifies under "Electronics Engineers, Except Computer" for prevailing-wage purposes.
DOL prevailing wage, 2026-27 wage year · Electronics Engineers, Except Computer (17-2072) · San Jose-Sunnyvale-Santa Clara, CA. Wage level is derived by USCIS from the offered wage, occupation and worksite; the occupation shown is inferred from the job title.
Employer immigration record
from this employer's Department of Labor filings
Files H-1B transfers
Sourced from Department of Labor LCA, PERM and prevailing-wage disclosure data. Employer matching is by name, so figures may be split across an employer's legal entities. Absence of a filing means none appears in our copy of the data, not that none exists.
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About the role
- You are the force multiplier scaling the team's capabilities and enabling faster, better tapeouts.
- This role is fully on-site at our San Jose, CA location.
Responsibilities
- Define, develop, and maintain reusable physical design flows spanning synthesis, place-and-route, extraction, STA, and EMIR
- Own the end-to-end RTL-to-GDSII flow infrastructure across multi-vendor toolchains (Cadence Innovus, Tempus, Voltus, Pegasus
- Integrate and maintain DRC/LVS/extraction runsets and ensure consistency with foundry requirements
- Build and enhance automation scripts and infrastructure to manage large-scale multi-corner/multi-mode STA and EMIR runs with efficient partitioning and resource usage
- Develop QoR optimization frameworks and tracking methodologies to measure and improve design quality across programs
- Partner with IT and compute infrastructure teams to optimize job scheduling, storage, and compute resource utilization
- Support physical design engineers with flow issues, tool configurations, and methodology guidance
- Drive adoption of flow improvements across the team, including training and documentation
Requirements
- 8+ years of experience in physical design methodology, CAD, or flow development for complex SoCs at advanced nodes (7nm and below)
- Strong knowledge of synthesis, place-and-route, extraction, STA, and equivalence checking flows
- Experience with both Cadence (Innovus, Tempus, Voltus, Pegasus) and Synopsys (Fusion Compiler, PrimeTime, StarRC, ICC2) toolchains
- Ability to work independently with strong prioritization and a results-driven mindset
Nice to have
- Knowledge of agentic AI solutions for EDA automation
- Experience with CI/CD integration for physical design flows
- Familiarity with compute farm management and job scheduling optimization
- Knowledge of advanced packaging or multi-die integration flows
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field
- Masters Preferred.
Skills
- Labs (NASDAQ:
- ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions.
- Discover more at www.asteralabs.com.
Compensation
- The base salary range is $185,000 to $240,000 depending on experience, level, and business need.
This listing is sourced directly from Astera Labs Inc.'s careers page and normalized into a canonical job model.