Altera

Altera

CPU Design Engineer

San Jose, California, United States · Mid

Sponsorship not specified$133k-$193kDetected 22 days ago
PythonBashFPGAVerilogElectrical EngineeringSignal Processing

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odds of building a lasting career here

61Sponsors, lottery-bound
Cap-exempt (no lottery)0
Sponsors this role90
Entry-level history0
PERM / green-card track0
Lottery odds (Level IV)94
Fits your clock70

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About the role

  • You will directly shape the future of Altera's embedded processor roadmaps, such as our RISC-V-based Nios V ecosystem, enabling customers to deploy flexible, high-efficiency processing directly into programmable logic.
  • PPA Optimization for Programmable Logic: Maximize Performance, Power, and Area (PPA) by optimizing processor pipelines around FPGA-specific constraints, utilizing Adaptive Logic Modules (ALMs), M20K/MLAB memory blocks, and specialized DSP columns.
  • The pay range below is for Bay Area California only.

Responsibilities

  • FPGA-Targeted RTL Design: Micro-architect, design, and implement Soft CPU cores (using SystemVerilog/Verilog) intentionally structured to map efficiently onto Altera FPGA architectures
  • FPGA Synthesis & Timing Closure: Drive the design through Altera's proprietary tool flows, managing floorplanning, placement constraints, and aggressive timing closure at high frequencies.
  • Customization & Extensibility: Implement features allowing for highly configurable soft cores, including optional instruction set extensions, custom instructions, and variable cache configurations.
  • Verification & Validation: Collaborate with Design Verification (DV) teams to build robust simulation environments and actively participate in hardware validation using Altera development boards.
  • We are seeking an innovative Soft CPU Design Engineer to join our IP Engineering team at our Altera Headquarters in San Jose, CA.
  • In this specialized role, you will be responsible for the micro-architecture, RTL design, and implementation of high-performance, area-efficient Soft CPU cores.
  • Unlike traditional ASIC design, your focus will be entirely on architecting processor pipelines that are natively optimized to leverage Altera FPGA architectures (including ALMs, embedded memory blocks, and DSP slices).
  • FPGA-Targeted RTL Design:
  • Micro-architect, design, and implement Soft CPU cores (using SystemVerilog/Verilog) intentionally structured to map efficiently onto Altera FPGA architectures
  • Drive the design through Altera's proprietary tool flows, managing floorplanning, placement constraints, and aggressive timing closure at high frequencies.

Requirements

  • Required Skills & Qualifications
  • Core Experience: 3+ years of digital design experience with a specific focus on CPU/Processor RTL design and FPGA implementation.
  • Languages: Advanced proficiency in SystemVerilog or Verilog for FPGA synthesis.
  • Architectural Knowledge: Strong understanding of processor pipeline design, hazard handling, branch prediction, and memory hierarchy (caches, tightly-coupled memories).
  • FPGA Tooling: Deep hands-on proficiency with Altera Quartus Prime Pro, including advanced components like Platform Designer (Qsys), TimeQuest Timing Analyzer, and Signal Tap or similar EDA software.
  • Applicants must be eligible for any required U.S. export authorizations.
  • Education: Bachelor's, Master's, or Ph.D. in Electrical Engineering, Computer Engineering, or a related technical discipline.

Nice to have

  • In-depth familiarity with the open-source RISC-V ISA specification and custom instruction insertion.
  • Experience with standard FPGA on-chip interfaces like Avalon Memory-Mapped / Streaming and AMBA AXI interfaces.
  • Knowledge of compiler toolchains (GCC, LLVM), assembly programming, and embedded C debugging.
  • Proficiency in Python, Tcl, or Shell scripting to automate FPGA compilation and regression workflows.
  • Shift 1 (United States of America)
  • San Jose, California, United States
  • Posting Statement:

Skills

  • Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc.

Compensation

  • The pay range below is for Bay Area California only.
  • Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc.
  • We also offer incentive opportunities that reward employees based on individual and company performance.

Company info

  • We also offer incentive opportunities that reward employees based on individual and company performance.
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