OLIX
Senior/Staff Design for Test Engineer
Austin, TX · Staff+
Sponsorship not specifiedDetected 55 days ago
PythonMachine LearningVHDLVerilogCommunicationCollaboration
About the role
- You will join a multidisciplinary group creating next-generation accelerators where digital, optical, and mixed-signal domains intersect.
Responsibilities
- Lead the integration and verification of all DFT features, including Scan, JTAG, Boundary Scan, and Memory BIST, ensuring adherence to industrial standards and sign-off criteria.
- Drive RTL development (SystemVerilog / Verilog / VHDL) with a focus on DFT architecture, including synthesis constraints for test structures, and collaborate on formal and constrained-random verification of DFT logic.
- Collaborate with mixed-signal and software teams to define and optimise DFT interfaces, test modes, and firmware abstractions for test control and diagnosis.
- Mentor junior engineers, lead DFT design reviews, and champion best-practice methodologies for testability and debug across the ASIC development lifecycle.
Requirements
- Proficiency using Python/Tcl scripting for DFT flow automation, pattern generation/management, and silicon debug/bring-up.
- Demonstrated proficiency with DFT flows: compression techniques, EDT, JTAG/IEEE 1149.1/1687, and managing large pattern sets.
Nice to have
- Tape‑out experience at 22 nm or below.
- Knowledge of high-speed SerDes or HBM/DDR DFT challenges.
- Familiarity with AI/ML workloads or systolic arrays and their implications for DFT.
- Contributions to open‑source DFT tools or verification frameworks.
- You're not just joining the mission
- you're owning a piece of it
- Due to U.S. export control regulations, candidates' eligibility to work at OLIX depends on their most recent citizenship or permanent residency status.
- Applicants who have subsequently obtained citizenship or permanent residency in another country not subject to these restrictions may still be eligible.
Skills
- Expertise with industry‑standard
- Scan insertion, ATPG, pattern simulation (gate-level), fault modeling, and diagnosis tools.
Compensation
- Commensurate with your experience, skills, and location
Benefits
- Employer-contributed retirement plans to help you build long-term financial security.
- Meaningful stock options.
- To minimise your commute and maximise your life, we offer an annual Living-Local Bonus if your residence is within 20 minutes of the office
- Architect, own, and implement the comprehensive Design-for-Test (DFT) strategy for complex high-throughput digital pipelines in advanced CMOS nodes, ensuring high test coverage and efficient test execution.
- Partner with the test engineering team to develop, validate, and optimize ATE-compatible test patterns (stuck-at, transition, bridging, etc.) to achieve aggressive fault coverage and maximise manufacturing yield.
- 7+ years of hands‑on DFT architecture, implementation, and verification for high‑performance ASICs or SoCs, including ownership of at least one product with comprehensive DFT coverage.
Visa & Work Authorization
- export control regulations, candidates' eligibility to work at OLIX depends on their most recent citizenship or permanent residency status
This listing is sourced directly from OLIX's careers page and normalized into a canonical job model.