Celerocommunicationsinc

Principal PLL Design Engineer

Irvine, CA or San Jose, CA · Principal

Sponsorship not specified$150k-$250kDetected 6 days ago

MATLABNode.jsCadenceElectrical EngineeringCommunication

About the role

Are you a PLL Design Engineer passionate about developing the high-speed clocking technology that will power the next generation of AI infrastructure? Join our fast-growing semiconductor startup and help deliver disruptive High-Speed Interconnect solutions for tomorrow's optical networks.
We are seeking a High-Speed CMOS PLL Analog Design Engineer to play a key role in the architecture and design of advanced clocking circuits for next-generation optical transceivers, high-speed SerDes, and high-performance ADC/DAC systems. In this role, you will architect and design state-of-the-art PLLs for industry-leading transceivers, working alongside a

Architect, design and simulate analog/mixed-signal PLL building blocks (VCOs, charge pumps, dividers, PFDs, Loop Filters) at transistor level using tools like Cadence Virtuoso and Spectre
Deep understanding of phase noise analysis, VCO design, LDOs and supporting circuitry associated with PLLs

Master's degree and/or PhD in Electrical Engineering or related fields with 5+ years of relevant experience in PLL design, and production level tape-out experience
Must have extensive experience with advanced node technologies (16nm/12nm, 7nm, 5nm, 3nm, 2nm processes)

$150,000 - $250,000 (The final offer will be determined based on job-related skills, experience, qualifications, and location.)

This listing is sourced directly from Celerocommunicationsinc's careers page and normalized into a canonical job model.