Microsoft

Microsoft

Principal Physical Design Engineer

Raleigh, NC, US · Principal

Sponsorship not specifiedDetected 9 hours ago
Data AnalysisElectrical EngineeringLeadershipCommunicationProblem Solving

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odds of building a lasting career here

42Risky
Cap-exempt (no lottery)0
Sponsors this role100
Entry-level history0
PERM / green-card track0
Lottery odds40
Fits your clock70

Thin sponsorship signal and lottery-bound. A low-probability bet with your clock running. Prioritize cap-exempt roles and proven entry-level sponsors first.

Lottery odds assume a STEM candidate.

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Employer immigration record

from this employer's Department of Labor filings

Green-card filing pattern in this occupation

Context, not a finding about this posting: of this employer's 17 green-card filings in this occupation, 100% were for a worker who already held the job.

Green-card follow-through: 87%

Of 741 labor certifications old enough to have been used, 96 expired without the employer filing the next step. Median time from filing to decision: 439 days.97% of their filings were for a worker who already held the job.Only certifications past the 180-day window are counted — recent ones cannot have expired yet.

Reported a layoff in this occupation

In a green-card filing decided 2026-01-14, this employer stated it had laid off workers in Electronics Engineers, Except Computer (WA) during the preceding six months.Describes the period before that filing, not necessarily today. Unlike WARN notices this is occupation-specific and federal.

Files H-1B transfers

1131 transfer filings in the last year, covering 1131 workers. Median labor-condition decision: 7 days. An employer that already files transfers is one that can take over an existing H-1B.

Sourced from Department of Labor LCA, PERM and prevailing-wage disclosure data. Employer matching is by name, so figures may be split across an employer's legal entities. Absence of a filing means none appears in our copy of the data, not that none exists.

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About the role

  • Responsible for clock construction and CTS.
  • Clear communications on project status & planning.

Responsibilities

  • Lead and Execute end-to-end PD flow from synthesis through place-and-route for multiple designs, ensuring completion of all signoff stages including timing, physical verification, EMIR, formal equivalence, and low-power verification.
  • Drive methodology exploration activities to optimize SOC blocks for clock construction and related methodology.
  • Coordinate with CAD, RTL/Design teams/DFT, Architecture team, Power & Performance team, Technology team & other internal/external partners as essential.
  • Responsible for RTL to GDS implementation and ownership in Physical Design domain.
  • Influence design tools, flows, and methodologies in construction, signoff, and optimization through a data-driven approach.
  • Demonstrate leadership and technical expertise across various domains of Physical Design.
  • Track record in Physical Design domain implementing designs through synthesis, floorplanning, place and route, extraction, timing, and physical verification.
  • Experience in low power design methodology for SOC Understanding of SOC or subsystem design trade-offs across power, performance, and area (PPA).
  • Familiarity with various clock construction strategies for high speed designs Demonstrate technical expertise in all aspects of Physical Design, from synthesis to place and route of partitions through all signoff including timing signoff, physical verification, EMIR signoff, Formal Equivalence, and Low Power Verification.
  • Own complete PD execution of medium to large-size SOC block.

Requirements

  • 20+ years of experience in Physical design Production silicon tape-outs experience in advanced foundry process nodes.
  • Be fully hands-on in technical domain ownerships as individual contributor and collaborate cross-team as required.

This listing is sourced directly from Microsoft's careers page and normalized into a canonical job model.