Micron
HBM SoC Physical Design Engineer
Folsom, CA · Full-time
Sponsorship not specified$121k-$205kDetected 6 hours ago
Agentic AICadenceElectrical EngineeringCommunication
> stay_score
odds of building a lasting career here
64Sponsors, lottery-bound
Cap-exempt (no lottery)0
Sponsors this role100
Entry-level history0
PERM / green-card track0
Lottery odds (Level IV)94
Fits your clock70
Sponsors, but it's cap-subject — you still face the weighted lottery (~61% per draw at Level IV). Good if you win; have a cap-exempt backup on your list.
Lottery odds assume a STEM candidate.
Personalize to your clock →> community_outcomes
No reports yet — be the first to help the next applicant.
About the role
- Our vision is to transform how the world uses information to enrich life for all.
- Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.
- You will also work on efforts to enable and integrate AI-driven tools and AI-enabled workflows into the team's methodologies.
Responsibilities
- Own physical implementation for SoC blocks and/or top-level, including floor-planning, placement, CTS, routing, and physical optimization to meet PPA targets.
- Drive timing closure (setup/hold) across multi-mode/multi-corner (MMMC) scenarios
- partner with RTL, architecture, and STA/signoff to converge designs.
- Integrate and implement complex IP (e.g., controllers, microcontrollers, NOC, interfaces, MBIST/DFT logic, buffers, PHY‑adjacent logic) with focus on robust physical integration and timing/power integrity.
- Perform and/or coordinate physical signoff, including DRC/LVS, IR drop/EM, and timing signoff, addressing violations efficiently.
- Partner with DFT teams to ensure scan/MBIST requirements are physically realizable and do not compromise PPA or schedule.
- Work with packaging, assembly, test, probe, and manufacturing collaborators to ensure builds meet manufacturability and quality requirements.
- Support tape-out execution (checklists, ECO flows, signoff reviews) and contribute to post-silicon debug by correlating silicon behavior with PD/STA/power analysis.
- Drive timing closure (setup/hold) across multi-mode/multi-corner (MMMC) scenarios; partner with RTL, architecture, and STA/signoff to converge designs.
Requirements
- Proficiency with industry EDA tools (e.g., Cadence Innovus/Tempus, Synopsys ICC2/PrimeTime, Siemens Calibre or equivalent).
- Experience with power intent and power delivery considerations (e.g., UPF/CPF concepts, power grid planning, power gating implications).
- Familiarity with physical verification/signoff concepts: DRC, LVS, ERC, parasitic extraction awareness, and signoff handoff quality.
Nice to have
- Experience with HBM / DRAM adjacent SoC designs, or memory-subsystem-heavy SoCs.
- Bachelor's or master's degree in electrical engineering, Computer Engineering, or a related field.
- Minimum 3 years of experience in a related field.
- $121,000.00 - $205,000.00 a year
- The pay scale is subject to change depending on business needs.
- Micron is proud to be an equal opportunity workplace and is an affirmative action employer.
- To learn about your right to work click here.
- To learn more about Micron, please visit micron.com/careers
Compensation
- The US base salary range that Micron Technology estimates it could pay for this full-time position is:
Benefits
- Additional compensation may include benefits, bonuses and equity.
Company info
- We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget.
Visa & Work Authorization
- ve consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protec
This listing is sourced directly from Micron's careers page and normalized into a canonical job model.