Inferact

Inferact

Member of Technical Staff, TPU Performance Engineering

San Francisco · Staff+

H1B sponsorship available$200k-$400kDetected 127 days ago
Machine LearningPyTorchLLMsLogistics

Stay score

odds of building a lasting career here

59Sponsors, lottery-bound
Cap-exempt (no lottery)0
Sponsors this role80
Entry-level history0
PERM / green-card track0
Lottery odds (Level IV)94
Fits your clock70

Sponsors, but it's cap-subject — you still face the weighted lottery (~61% per draw at Level IV). Good if you win; have a cap-exempt backup on your list.

Lottery odds assume a STEM candidate.

Personalize to your clock →

H-1B wage level

the lottery is wage-weighted — each level is one more entry

Level III · 3×
Level I$137,0931 entry
Level II$165,1312 entries
Level III$193,1493 entries
Level IV$221,1874 entries

$21,187 more — $221,187 — moves this role to Level IV and 4 lottery entries. That figure is inside the range the employer already advertised.

Based on the DOL prevailing wage for this occupation and worksite, a base salary of $221,187 would place this position at wage Level IV. That figure is within the posted range, and I'd like to target it. This role classifies under "Software Developers" for prevailing-wage purposes.

DOL prevailing wage, 2026-27 wage year · Software Developers (15-1252) · San Francisco-Oakland-Fremont, CA. Wage level is derived by USCIS from the offered wage, occupation and worksite; the occupation shown is inferred from the job title.

Employer immigration record

from this employer's Department of Labor filings

Files H-1B transfers

3 transfer filings in the last year, covering 3 workers. Median labor-condition decision: 7 days. An employer that already files transfers is one that can take over an existing H-1B.

Sourced from Department of Labor LCA, PERM and prevailing-wage disclosure data. Employer matching is by name, so figures may be split across an employer's legal entities. Absence of a filing means none appears in our copy of the data, not that none exists.

Community outcomes

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About the role

  • We're looking for a TPU performance engineer to make vLLM a first-class inference engine on Google TPUs.
  • You'll work at the boundary of inference systems, kernels, compilers, and hardware architecture, improving production-relevant model serving on TPU with clear correctness, latency, and throughput benchmarks.

Responsibilities

  • You'll build and optimize TPU backends, compiler integrations, runtime paths, and benchmarking infrastructure using JAX, XLA, Pallas, and related tooling so vLLM can deliver frontier inference performance on TPU hardware.
  • Your work will help make TPU support in vLLM usable, fast, benchmarked, and maintainable.

Requirements

  • Experience optimizing ML kernels or inference paths such as attention, GEMM, sampling, KV cache, fused kernels, or backend runtime paths.
  • Strong performance profiling and benchmarking skills, with the ability to use measurements, compiler artifacts, correctness tests, and reproducible benchmarks to guide optimization work.

Nice to have

  • Experience with vLLM, SGLang, TensorRT-LLM, XLA-based serving, or other LLM inference systems.
  • Familiarity with batching, KV cache, decoding, serving tradeoffs, and backend performance constraints in production inference systems.
  • Experience with compiler technologies such as XLA, MLIR, LLVM, Pallas, or other kernel DSLs, including lowering, fusion, and backend code generation.
  • Knowledge of quantization methods such as INT8, FP8, mixed precision, or TPU-specific numeric formats, including accuracy and performance tradeoffs.
  • Contributed to vLLM, JAX/XLA, Pallas, PyTorch/XLA, compiler projects, or other open-source ML infrastructure.
  • Built TPU benchmarking infrastructure or automated performance regression detection for accelerator workloads.
  • Worked directly with Google TPU ecosystem stakeholders, accelerator platform teams, or early-access programs to ship backend, compiler, or inference performance improvements.
  • Visa sponsorship: We sponsor visas on a case-by-case basis.

Skills

  • Skills and Qualifications

Compensation

  • Depending on background, skills, and experience, the expected annual salary range for this position is $200,000 - $400,000 USD + equity.

Benefits

  • Inferact offers generous health, dental, and vision benefits as well as 401(k) company match.

Company info

  • About the Role We're looking for a TPU performance engineer to make vLLM a first-class inference engine on Google TPUs.
  • Inferact's mission is to grow vLLM as the world's AI inference engine and accelerate AI progress by making inference cheaper and faster.
  • Founded by the creators and core maintainers of vLLM, we sit at the intersection of models and hardware, a position that took years to build.

Visa & Work Authorization

  • We sponsor visas on a case-by-case basis.

This listing is sourced directly from Inferact's careers page and normalized into a canonical job model.