Astera Labs Inc.
Senior Digital Design Engineer, IP and Methodology
San Jose, California, United States · Senior
Sponsorship not specified$135k-$195kDetected 4 days ago
PythonCybersecurityCadenceVerilogEmbedded SystemsElectrical Engineering
About the role
- Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions.
- In this role, you'll focus on CPU subsystem development and security architecture, working on complex blocks from micro-architecture through silicon bring-up.
- This is an opportunity to shape the security and compute foundations of connectivity solutions enabling rack-scale AI infrastructure at hyperscale.
Responsibilities
- Own the RTL implementation of complex digital designs from micro-architecture through sign-off
- Design and implement CPU subsystems and embedded processor interfaces
- Develop security-focused digital blocks including secure boot, cryptographic engines, and trusted execution environments
- Collaborate with verification teams to review test plans and debug issues
- Support efforts to achieve timing closure and implement Design-for-Test (DFT) features
- Accountable for quality and overall design success with the support of senior engineers
- Contribute to design infrastructure that improves team productivity and design quality
Requirements
- Bachelor's degree in Electrical Engineering or equivalent
- 3+ years of experience developing SoC/silicon products in Server, Storage, and/or Networking markets
- Expertise in RTL coding with SystemVerilog and synthesis with Synopsys or Cadence
- Experience with CPU subsystem design or embedded processor integration (RISC-V, ARM, or similar architectures)
- Experience with clocking, CDC, and RDC methodologies
- Proficiency in SystemVerilog and Python in a production environment
Nice to have
- Experience designing or integrating security IP (cryptographic accelerators, secure enclaves, key management)
- Familiarity with high-speed protocols-PCIe Gen 6/7, Ethernet, UALink, or UCI
- Experience with CMOS nodes (≤7nm)
- Exposure to embedded firmware development or secure firmware boot flows
- Experience with functional and formal verification at block and chip level
- Familiarity with UVM-based verification methodologies
Skills
- RTL Design & Implementation
- Verification & Quality
- Methodology & Automation
- Scripting and automation for ASIC methodology improvement
Compensation
- Base salary range is $135,000 to $195,000 depending on experience, level, and business need.
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