Neuralink

Neuralink

Analog and Mixed-Signal IC Design Engineer Intern

South San Francisco, California, United States · Intern · Internship

Sponsorship not specifiedDetected 21 days ago
ExcelVerilogElectrical EngineeringResearchCommunication

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Cap-exempt (no lottery)0
Sponsors this role90
Entry-level history0
PERM / green-card track0
Lottery odds40
Fits your clock70

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About the role

  • These devices allow us to restore movement to the paralyzed, restore sight to the blind, and revolutionize how humans interact with their digital world.
  • We want to work with exceptional people, and, to the extent that you excel, we want you to take on more responsibility and help all of us succeed.

Responsibilities

  • Defines verification plan for a portion of IP or chip and runs complex simulations and analyses (e.g., power, performance, linearity, yield) on designs
  • Designs, programs, and runs complex tests and reviews tests of other team members; ensures bugs and other issues are identified and appropriately analyzed
  • The Analog and Mixed-Signal IC Design Engineer Intern will be responsible for analog and mixed-signal chip design, from circuit design to layout and verification.
  • Define and implement innovative and optimal analog and mixed signal circuit architectures and transistor-level circuit solutions to achieve a variety of challenging noise, mismatch, distortion, power consumption, and cost requirements
  • The Brain Interfaces Soc Department delivers chip architecture and silicon implementation of neural recording and stimulation system-on-chip (SoC) for high-bandwidth brain-machine interface applications.
  • To accelerate our pathway to human ready brain-computer interfaces, you will have the opportunity to partner with our electrical, microfabrication, chip designers, neuro and mechanical engineers.

Requirements

  • Minimum 1 years of experience in analog/mixed-signal integrated CMOS circuit design for a specific area (e.g., delta-sigma ADC, SAR ADC, DAC, VCO, PLL, DLL, Audio CODEC and Class D audio amplifier, high speed PHY & SERDES) with a successful track record of silicon validation
  • Minimum 3 months experience of application of technical skills outside of the classroom (examples: laboratory, research, extracurricular project teams, open source contributions, volunteering, personal projects or prior internship/work experience)
  • The ideal candidates are people who get excited about building things, are highly analytical, and enjoy tackling new problems regularly

Nice to have

  • Skills in scripting and automation for complex simulation scenarios
  • Experience in lab testing of high-precision analog and mixed-signal ICs
  • Functional modeling experience and logic verification with Verilog AMS and SystemVerilog
  • Experience with design for high-volume production
  • An opportunity to change the world and work with some of the smartest and most talented experts from different fields
  • Growth potential
  • we rapidly advance team members who have an outsized impact
  • 401(k) plan *Interns initially excluded until they work 1,000 hours

Compensation

  • California Hourly Rate:

Benefits

  • Full-time employees are eligible for the following benefits listed below.
  • Excellent medical, dental, and vision insurance through a PPO plan
  • Commuter benefits
  • Equity (RSUs) *Temporary Employees & Interns excluded
  • Parental leave *Temporary Employees & Interns excluded
  • Flexible time off *Temporary Employees & Interns excluded

Company info

  • We are creating devices that enable a bi-directional interface with the brain.
  • We are looking for Analog and Mixed-Signal IC Design Engineer Interns who are interested in architecting and implementing innovative solutions with high energy-efficiency and compact silicon footprint and who thrive with the autonomy to propose creative approaches to problems.
  • We have crafted a team of exceptional engineers whose mission is to push the frontiers of what is possible today and define the future.

This listing is sourced directly from Neuralink's careers page and normalized into a canonical job model.