Astera Labs Inc.
Senior Design Verification Engineer
Toronto, Ontario, Canada · Senior
Stay score
odds of building a lasting career here
Thin sponsorship signal and lottery-bound. A low-probability bet with your clock running. Prioritize cap-exempt roles and proven entry-level sponsors first.
Lottery odds assume a STEM candidate.
Personalize to your clock →Employer immigration record
from this employer's Department of Labor filings
Files H-1B transfers
Sourced from Department of Labor LCA, PERM and prevailing-wage disclosure data. Employer matching is by name, so figures may be split across an employer's legal entities. Absence of a filing means none appears in our copy of the data, not that none exists.
Community outcomes
No reports yet — be the first to help the next applicant.
About the role
- This is an opportunity to contribute across the verification lifecycle at a hyper-growth connectivity company.
Responsibilities
- Build and maintain UVM-based verification environments using SystemVerilog and C/C++ integration through DPI/PLI.
- Translate design specifications into verification plans, test strategies, and reusable test sequences.
- Develop VIP abstraction layers that simplify and scale verification across projects and platforms.
- Create directed and constrained-random tests, transaction-level sequences, and user-controlled random constraints.
- Collaborate with RTL designers and other engineers to isolate, debug, and resolve failures across simulation, co-simulation, and FPGA-based emulation.
- Apply third-party verification IP to validate protocols including PCIe, Ethernet, InfiniBand, DDR, NVMe, and USB.
- Contribute to technical reviews, communicate verification status clearly, and manage priorities across multiple deliverables.
- As a Senior Design Verification Engineer, you will help build and validate complex connectivity silicon that enables the next generation of AI infrastructure.
- You will develop scalable verification environments, integrate UVM and C/C++ workflows, and partner closely with RTL designers to identify and resolve issues across simulation, co-simulation, and emulation.
Requirements
- Bachelor's degree in Electrical Engineering or a related field.
- 5 years of experience developing or verifying complex SoC or silicon pro
Skills
- Verification Architecture and Planning
- Stimulus, Assertions, and Coverage
- Automate verification infrastructure and regression workflows using Python or Perl.
- Debug and Cross-Functional Collaboration
Benefits
- Write assertions and cover, analyze coverage data, and drive closure against verification goals.
This listing is sourced directly from Astera Labs Inc.'s careers page and normalized into a canonical job model.