Globalhr

Sr. Principal Electrical Engineer - FPGA/ASIC Team (Onsite)

US-IA-CEDAR RAPIDS-121 ~ 350 Collins Rd NE ~ BLDG 121 · Principal

No sponsorshipDetected 4 days ago

PythonC++LinuxCybersecurityProduct ManagementFPGAVHDLVerilogAvionicsDO-254ResearchLeadershipCommunication

About the role

Together, we push the boundaries of known science and find new ways to connect and protect our world.
Join us and help shape the future of aerospace and defense.
We provide connectivity and managed data services to ensure safety and seamless communication for passengers, crews, and militaries, from aircraft and airports to air traffic management.

ASIC/FPGA/SoPC digital architecture development and design.
Develop RTL design code and simulation in VHDL, Verilog, and/or SystemVerilog.
Create UVM constrained random environments using SystemVerilog.
Create placement and timing constraints.
Perform synthesis, place and route.
Perform static timing analysis, linting analysis, LEC, and clock-domain-crossing analysis.
Perform ASIC/FPGA/SoPC verification using inspection, analysis, simulation, and test methods.
Create engineering bids and support RFIs and RFPs.
May perform the duties of a project engineer.
Recommend new tools and practices for continuous improvement in the group's ASIC/FPGA design flow.

U.S. citizenship is required, as only U.S. citizens are authorized to access information under this program/contract.
Typically requires a degree in Science, Technology, Engineering or Mathematics (STEM) and minimum 10 years prior relevant experience or an Advanced Degree in a related field and minimum 7 years of experience
Experience writing RTL and test benches using VHDL, Verilog, or SystemVerilog.
Experience using FPGA specific tools (e.g. Questasim, Vivado, Libero, Synplify Pro, etc.).
Experience with data interfaces (PCIe, DDR, I2C, Ethernet, CDN, ARINC-429, etc.).
Experience with device level timing and clock domain crossing.
Experience with Linux (or Unix), scripting, C/C++, Python, and/or Perl.
None/Not Required Security Clearance Status:
Experience with UVM Constrained Random Methodology.
Experience with DO-254 processes and design assurance activities for ASIC, FPGA, and/or SoPC developments.
You Must Have:
Ability to work with minimal supervision, as part of a team of engineers with a variety of skills and backgrounds, located throughout the world and matrixed into projects with aggressive schedules and frequent milestones.
Qualifications We Prefer:
Familiarity with best practice chip-level verification techniques and languages (e.g. constrained random, functional coverage, code coverage, LEC, SystemVerilog).

Some of our competitive benefits package includes:
Medical, dental, and vision insurance
Three weeks of vacation for newly hired employees
Generous 401(k) plan that includes employer matching funds and separate employer retirement contribution, including a Lifetime Income Strategy option
Tuition reimbursement program
Life insurance and disability coverage
Birth, adoption, parental leave benefits
Ovia Health, fertility, and family planning
Autism Benefit
Healthy You Incentives, wellness rewards program
Teladoc Medical Experts, second opinion program
Avionics delivers advanced cockpit displays, vision systems, and comprehensive digital solutions for global government, commercial and business aviation customers.

Communicate well with a wide variety of individuals including Engineering, Program Management, internal leadership and customers.
And the bonds we form - with our customers and with each other -- propel us all higher, again and again.
Apply now and be part of the team that's redefining aerospace, every day.
As part of our commitment to maintaining a secure hiring process, candidates may be asked to attend select steps of the interview process in-person at one of our

This listing is sourced directly from Globalhr's careers page and normalized into a canonical job model.