Lumilens
Verification Engineer
San Jose
Sponsorship not specifiedDetected 16 days ago
PythonCloud PlatformsFPGAVerilog
About the role
- Guided by the verification plan and methodology, you take assigned blocks from testbench bring-up through coverage signoff, and help debug across simulation and emulation.
- It's a hands-on role with room to grow your scope as the team and the chip mature.
Responsibilities
- Build and extend UVM testbenches (agents, sequences, scoreboards) for assigned blocks and subsystems.
- Run regressions, triage failures, and help maintain the CI/regression flow.
- Support hardware-assisted verification - bring up and run tests on emulation / FPGA prototyping.
- Collaborate with the design, architecture, modelling, and DFT teams as your blocks move through the flow.
- Professional development opportunities and certification support
Skills
- About Lumilens
- This isn't incremental innovation, it's a ground-floor opportunity to rethink the optical layer from the silicon up.
Compensation
- Competitive salary commensurate with experience
Benefits
- Comprehensive benefits package including health, dental, and vision
- All qualified applicants will receive consideration without regard to race, color, religion, gender identity, sexual orientation, veteran status, disability, or any other legally protected status.
- develop functional coverage and drive it to closure.
- Verify the in-house engines against an algorithmic golden model, with programmable error injection and error-pattern coverage.
- Solid UVM/SystemVerilog; constrained-random and coverage-driven verification.
- Testbench development and coverage closure - building block/subsystem testbenches and driving functional + code coverage to closure.
Equal opportunity
- equal opportunity employer.
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This listing is sourced directly from Lumilens's careers page and normalized into a canonical job model.