Vailexa

Vailexa

Senior SRAM Layout Design Engineer

Santa Clara, CA · Senior

Sponsorship not specifiedDetected 30 days ago
Node.jsCadenceElectrical EngineeringCommunicationMentoring

Stay score

odds of building a lasting career here

37Risky
Cap-exempt (no lottery)0
Sponsors this role80
Entry-level history0
PERM / green-card track0
Lottery odds40
Fits your clock70

Thin sponsorship signal and lottery-bound. A low-probability bet with your clock running. Prioritize cap-exempt roles and proven entry-level sponsors first.

Lottery odds assume a STEM candidate.

Personalize to your clock →

Employer immigration record

from this employer's Department of Labor filings

Third-party placement is common here

40% of this employer's visa filings place the worker at a client company rather than at the employer itself, across 2 clients. Your visa, salary band and layoff exposure would follow the employer of record, not the client.Most common: MICRON · USAA.

Files H-1B transfers

2 transfer filings in the last year, covering 2 workers. Median labor-condition decision: 8 days. An employer that already files transfers is one that can take over an existing H-1B.

Sourced from Department of Labor LCA, PERM and prevailing-wage disclosure data. Employer matching is by name, so figures may be split across an employer's legal entities. Absence of a filing means none appears in our copy of the data, not that none exists.

Community outcomes

No reports yet — be the first to help the next applicant.

About the role

  • We are seeking a Senior SRAM Layout Design Engineer to own the complete custom layout process for SRAM bitcell arrays, memory periphery, test structures, and memory macros in advanced CMOS technologies at the leading edge of process scaling.
  • The role works closely with circuit design, PnR/integration, CAD, and foundry teams to deliver consistent, high-quality memory IP on advanced FinFET/GAA nodes, and includes reviewing layouts and mentoring junior engineers to raise layout quality and execution rigor across the team.

Responsibilities

  • Manage the complete custom layout process for SRAM bitcell arrays, memory periphery, test structures, and memory macros in advanced CMOS technologies.
  • Develop and improve floorplans for SRAM and memory blocks, covering array layout, periphery positioning, power grid design, routing channels, and macro assembly.
  • Support EM/IR review, power integrity, density/fill, DFM, dummy insertion, layout-dependent effects, and other requirements for tapeout.
  • Collaborate with circuit designers to convert schematics into layouts, ensuring matching, symmetry, shielding, parasitic targets, and reliability constraints are maintained.
  • Collaborate with PnR and integration teams to resolve top-level DRC/LVS, pin access, boundary, routing, power-grid, and macro-integration issues.
  • Implement and advance layout methodology, checklists, reusable practices, and quality standards for consistent memory IP delivery.
  • Collaborate with foundry, CAD, and methodology teams on rule interpretation, deck behavior, waivers, and advanced-node process constraints.
  • This is a senior individual-contributor role - you'll own and contribute blocks alongside an established team of leads, not manage one.

Requirements

  • Experience limited to 10nm or 7nm does not meet the bar for this role
  • Extensive experience in Cadence Virtuoso applied to custom layout creation and assessment.
  • Extensive experience in DRC/LVS debugging using Calibre, ICV, or similar physical verification tools.
  • Experience with floorplanning, block-level routing, macro assembly, pin planning, boundary/interface management, and top-level physical verification.
  • Direct familiarity with advanced-node layout limitations and layout-dependent phenomena, including LOD, density/fill, matching, symmetry, shielding, electromigration, IR drop, and DFM or similar expertise.
  • Clear communication, strong ownership, good judgment, and the ability to mentor other engineers.

Nice to have

  • Experience on TSMC's next-generation, beyond-3nm process nodes.
  • Knowledge of, or demonstrated motivation to learn, AI-assisted layout automation tools.
  • Ready to take the next step?
  • If you're excited about this role and ready to grow with a team that values ambition, ideas, and impact - we'd love to hear from you.
  • Carry out, debug, and complete DRC, LVS, ERC, antenna, and associated physical verification checks with tools such as Calibre, ICV, or similar workflows.
  • Review layouts, mentor junior engineers, and help raise layout quality and execution rigor across the team.
  • BSEE or equivalent experience.
  • Hands-on, personal ownership of custom digital SRAM layout - candidates must have directly executed the layout themselves, not simply overseen or reviewed it.
Apply directly at Vailexa →Create a free account for alerts like thisView Vailexa immigration profile

This listing is sourced directly from Vailexa's careers page and normalized into a canonical job model.