Unconventionalinc

AI Silicon, Junior Digital Design Engineer

Palo Alto, CA · Junior

Sponsorship not specifiedDetected 27 days ago

Machine LearningLLMsVerilogElectrical EngineeringCommunication

About the role

You will be responsible for driving invention, prototyping, and validation of the core components of our novel computing platform.

SoC Design & Integration:
Perform hands-on RTL design for SoC blocks and digital interfaces, focusing on meeting power, performance, and area (PPA) targets.
Implement and debug key digital interfaces to ensure system stability.
Implement advanced techniques for low-power design (clock gating, power domains)
Perform initial synthesis and formal verification (LEC) to ensure the design is routable and meets frequency targets.
Create block-level timing constraints
Design Verification (DV) Support:
Participate in the block-level verification plan and help develop a robust verification environment.

Strong Technical Expertise:
Design Flow Proficiency:
Familiarity with standard EDA tools for simulation, assertions, synthesis, linting, and clock domain crossing (CDC) analysis
The Mission: Tackle a fundamental problem that could redefine computing for the next 50 years.

Experience with UVM (Universal Verification Methodology) environments for basic debugging.
Knowledge of formal verification techniques.
Exposure to post-silicon bring-up and lab debugging using logic analyzers or oscilloscopes.
Experience with modern design methods, including generative AI code development platforms.
Experience integrating large analog mixed-signal blocks into larger subsystems.

Run and resolve RTL linting, Clock Domain Crossing (CDC), and Reset Domain Crossing (RDC) checks using industry standard tools.

A comprehensive package including best-in-class health benefits, 401k matching, truly unlimited PTO, and complimentary meals in our Palo Alto office.

This listing is sourced directly from Unconventionalinc's careers page and normalized into a canonical job model.