Samsung Semiconductor
Senior Physical Design Engineer
San Jose, California, United States · Senior
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odds of building a lasting career here
Sponsors, but it's cap-subject — you still face the weighted lottery (~61% per draw at Level IV). Good if you win; have a cap-exempt backup on your list.
Lottery odds assume a STEM candidate.
Personalize to your clock →H-1B wage level
the lottery is wage-weighted — each level is one more entry
$17,896 more — $155,896 — moves this role to Level II and 2 lottery entries. That figure is inside the range the employer already advertised.
Based on the DOL prevailing wage for this occupation and worksite, a base salary of $155,896 would place this position at wage Level II. That figure is within the posted range, and I'd like to target it. This role classifies under "Electronics Engineers, Except Computer" for prevailing-wage purposes.
DOL prevailing wage, 2026-27 wage year · Electronics Engineers, Except Computer (17-2072) · San Jose-Sunnyvale-Santa Clara, CA. Wage level is derived by USCIS from the offered wage, occupation and worksite; the occupation shown is inferred from the job title.
Employer immigration record
from this employer's Department of Labor filings
Green-card filing pattern in this occupation
Green-card intent detected
Green-card follow-through: 44%
Files H-1B transfers
Sourced from Department of Labor LCA, PERM and prevailing-wage disclosure data. Employer matching is by name, so figures may be split across an employer's legal entities. Absence of a filing means none appears in our copy of the data, not that none exists.
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About the role
- Please Note: To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period.
- Advancing the World's Technology Together Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more.
- We believe innovation and growth are driven by an inclusive culture and a diverse workforce.
Responsibilities
- Own the physical implementation of memory-centric computing IP and SoC partitions from RTL netlist to GDSII, including synthesis, floorplanning, placement, clock tree synthesis (CTS), and routing.
- Drive block- and full-chip-level PPA (performance, power, and area) convergence and timing closure across multiple process corners and operating modes.
- Develop floorplans, power delivery networks, and macro placement strategies for memory controllers, NoC, and high-bandwidth interconnect subsystems.
- Perform static timing analysis (STA), constraint development, and signoff, resolving setup/hold timing, IR-drop, electromigration, and signal integrity issues.
- Collaborate with RTL and verification engineers, providing physical feedback that informs design-for-PPA and floorplan-aware microarchitecture decisions.
- Make design decisions out of a large design trade-off space across performance, power, thermal, and cost.
- Develop and automate physical implementation flows and methodologies using Tcl/Python scripting and agentic AI tools and frameworks to improve turnaround time and quality of results.
- Communicate effectively with stakeholders, including users, partners, and management, to ensure that the designs are delivered on time and within budget.
- You're collaborative, building relationships, humbly offering support and openly welcoming approaches.
- We extend comprehensive accommodations throughout our recruiting processes for candidates with disabilities, long-term conditions, neurodivergent individuals, or those requiring pregnancy-related support.
Requirements
- Bachelor's with 5+ years, or Master's with 3+ years, or PhD's with 0+ years of industry experience.
- 5+ years of experience in physical design implementation - synthesis, floorplanning, place-and-route, clock tree synthesis, and timing closure - for complex ASIC/SoC designs.
- Proficiency with industry-standard EDA tools such as Synopsys Fusion Compiler/ICC2, Cadence Innovus, PrimeTime, and StarRC.
- Experience with static timing analysis and constraint (SDC) development, low-power design (UPF/CPF), and power, IR-drop, and electromigration analysis.
- Experience with physical verification (DRC, LVS, antenna) and tapeout on advanced FinFET process nodes.
- Experience implementing memory controllers, NoC, or high-speed interconnect IP and full-chip SoC integration.
- Proficiency in scripting (Tcl, Python, or Perl) for physical design flow automation.
- Experience in AI/ML workloads.
- Strong background in digital physical design and VLSI implementation.
- Strong analytical and problem-solving skills
- Excellent communication and interpersonal skills
- Ability to work independently and as part of a team
- You're inclusive, adapting your style to the situation and diverse global norms of our people.
- An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
Skills
- Advancing the World's Technology Together
- Please Note:
- Join us in our passion to shape the future of computing!
Compensation
- $138,000 - $206,000 USD
- Base Pay Range
Benefits
- This is in addition to our diverse package of benefits centered around the wellbeing of our employees and their loved ones.
- In addition to the usual Medical/Dental/Vision/401k, our inclusive rewards plan empowers our people to care for their whole selves.
- Enjoy Time Away You'll start with 4+ weeks of paid time off a year, plus holidays and sick leave, to rest and recharge.
- Care for Family Whatever family means to you, we want to support you along the way-including a stipend for fertility care or adoption, medical travel support, and virtual vet care for your fur babies.
- Prioritize Emotional Wellness With on-demand apps and free confidential therapy sessions, you'll have support no matter where you are.
- Embrace Flexibility Benefits are best when you have the space to use them.
- That's why we facilitate a flexible environment so you can find the right balance for you.
- Our onsite Café and gym, plus virtual classes, make it easier.
Company info
- What We Offer The pay range below is for all roles at this level across all US locations and functions.
- Our Commitment to Innovation and Fairness At Samsung Semiconductor, we use Artificial Intelligence (AI) tools in the recruitment process to enhance efficiency.
Equal opportunity
- Employment Policy
- Samsung Semiconductor takes pride in being an equal opportunity workplace dedicated to fostering an environment where all individuals feel valued and empowered to excel, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status.
- When selecting team members, we prioritize talent and qualities such as humility, kindness, and dedication.
- All candidates scheduled for an interview will receive guidance on requesting accommodations.
This listing is sourced directly from Samsung Semiconductor's careers page and normalized into a canonical job model.